Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: A clock generating circuit is operated in a closed-loop state to generate an output clock signal that is frequency-locked with respect to an oscillatory input signal. Upon detecting a frequency transition in the input signal, the clock generating circuit is switched from the closed-loop operating state to an open-loop operating state to enable the output clock signal to oscillate at a free-running frequency. A ratio between input signal frequency and the free-running frequency of the output clock signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output clock signal with respect to input signal.

Abstract: Provided is a startup circuit which allows a reference voltage generating circuit to start up and reach a stable equilibrium state in an extremely short period. The startup circuit is configured to hold voltage which is substantially the same as internal voltage of the reference voltage generating circuit in the stable equilibrium state even when power is not supplied to the startup circuit. The voltage is output from the startup circuit to the reference voltage generation circuit when the reference voltage generating circuit is started.

Abstract: An electronic component includes a switching device comprising a source, a gate, and a drain, the switching device having a predetermined device switching rate. The electronic component further includes a gate driver electrically connected to the gate and coupled between the source and the gate of the switching device, the gate driver configured to switch a gate voltage of the switching device at a gate driver switching rate. The gate driver is configured such that in operation, an output current of the gate driver cannot exceed a first current level, wherein the first current level is sufficiently small to provide a switching rate of the switching device in operation to be less than the predetermined device switching rate.

Abstract: An active combiner can have multiple output sections each with a corresponding input section or a single output section with multiple input sections. The output section can switch between mixer and amplifier modes, with or without variable gain, to modify an input signal from the input section. The input section has a sufficiently high impedance to substantially block the RF signal from other input sections from entering any of the other input sections. The output section has a sufficiently low impedance to receive the RF signal from the input sections.

Abstract: Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.

Abstract: A frequency dividing system, which comprises a control circuit, a first multiple input sharing input level triggering device, a first input level triggering group and a second input level triggering group. The first multiple input sharing input level triggering device receives a first frequency dividing signal to generate a feedback signal according to a level of a first clock signal, or receives a second frequency dividing signal to generate the feedback signal according to a level of a second clock signal. The first/second input level triggering group generates the first/second frequency dividing signal to the first multiple input sharing input level triggering device according to the feedback signal if active; and outputs a fixed voltage to the first multiple input sharing input level triggering device if non-active.

Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.

Abstract: A frequency divider circuit includes an adder circuit, multiplexer circuits, and a phase interpolator circuit. The adder circuit generates a summed value. The multiplexer circuits receive first periodic signals and generate second periodic signals by selecting among the first periodic signals based on the summed value. The phase interpolator circuit generates a third periodic signal using a weighted average of the second periodic signals that is determined based on the summed value.

Abstract: Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.

Abstract: A signal transmission cable includes a multi-layer parallel transmission path, a single-layer parallel transmission path, and a single-layer/multi-layer conversion section. The multi-layer parallel transmission path includes two or more dielectric waveguides stacked in upper and lower directions. Each dielectric waveguide includes a dielectric layer formed of a dielectric substance, two conductive layers formed to sandwich the dielectric layer, and two quasi-conductive walls. The two quasi-conductive walls include a plurality of via-holes electrically connected to the two conductive layers. The dielectric waveguides are arranged sharing the conductive layers in contact in the upper and lower directions. The single-layer parallel transmission path includes the two or more dielectric waveguides arranged in left- and right-hand directions on the same dielectric layer and conductive layer.

Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

Abstract: The present invention provides an overvoltage protection method for backlight drive circuit of 2D/3D mode and a backlight drive circuit using the method. The method includes: providing a liquid crystal display, the liquid crystal display having a 2D mode and a 3D mode, the liquid crystal display including a backlight drive circuit; the backlight drive circuit using the first overvoltage protection voltage level as an overvoltage protection voltage level when the liquid crystal display is set in the 2D mode; and the backlight drive circuit using the second the overvoltage protection voltage level as an overvoltage protection voltage level when the liquid crystal display is set in the 3D mode, the second the overvoltage protection voltage level being greater than the first overvoltage protection voltage level. Different overvoltage protection voltage levels are provided for the 2D and 3D modes so as to alleviate impact on components by over voltage.

Abstract: The present invention relates to a waveguide E-plane filter component (1) comprising a first and second main part (2: 4) with a corresponding first and second waveguide section part (3, 5). The main parts (2, 4) are arranged to be mounted to each other, such that an open side (8) of the first waveguide section part (3) is arranged to face an open side (9) of the second waveguide section part (5). The E-plane filter component (1) further comprises at least one electrically conducting foil (10, 11) that is arranged to be placed between the main part (2, 4), Said foil (10, 11) have a longitudinal extension (L) and comprises a filter part (12) that is arranged to run between the waveguide section parts (3, 5), and is divided into a first filter part (13) and a second filter part (14) by an imaginary symmetry line (15) running along the longitudinal extension (L) in the middle of the filter part (12).

Abstract: A delay circuit includes at least one main inverter configured to receive an input signal and output a delayed output signal and at least one switchable inverter connected in parallel with the main inverter circuit. The switchable inverter is configured to decrease a delay between the input signal and the delayed output signal based on the switchable inverter being turned on.

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract: A quantizer takes an analog signal as input and produces a quantized signal for output. The quantizer includes a shoot-through current detection unit and a feedback unit. The shoot-through current detection unit is configured to detect a shoot-through current flowing through the quantizer. The feedback unit is configured to feed back a signal from the shoot-through current detection unit and control an electric charge stored at an input of the quantizer.

Abstract: A polarization coupler includes: connector waveguide that connects circular waveguide with quadrangular waveguide arranged in an axial direction of circular waveguide and having short side shorter than an inner diameter of circular waveguide; flat conductor wall formed over connector and circular waveguides, and dividing the inside of connector and circular waveguides arranged parallel to an extending direction of long side of quadrangular waveguide; first inclined surface formed on inner wall of connector waveguide at a position facing one surface of conductor wall, and inclined toward conductor wall as coming closer to quadrangular waveguide; second inclined surface formed on the inner wall of connector waveguide at a position facing the other surface of conductor wall, and inclined toward conductor wall as coming closer to quadrangular waveguide; and coupling hole, formed in circular waveguide, for extracting one polarization-divided by conductor wall out of electromagnetic waves propagated through circula

Abstract: A circuit for routing signals in an integrated circuit is disclosed. The circuit comprises a path having a plurality of registers coupled in series and including a source register, a destination register and at least one intermediate register; a clock generator generating a clock signal; and a delay element coupled to receive the clock signal and generate a delayed clock signal, wherein the delayed clock signal is coupled to a clock input of the at least one intermediate register. A method of routing signals in an integrated circuit is also disclosed.

Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.