Abstract: A data persistence control apparatus for an RFID tag is provided. The apparatus includes a capacitor to be charged, a charge circuit to charge the capacitor, a discharge circuit to discharge the capacitor, a switch switched on to electrically connect the charge circuit to the capacitor or the discharge circuit to the capacitor, and an output circuit to output a logic high signal or a logic low signal according to an input voltage determined based on a discharged degree of the capacitor.

Abstract: A ramp generator circuit for generating sawtooth waveforms based on a clock signal may include an operational amplifier, a first switched capacitor device within a first feedback path of the operational amplifier, and a first plurality of switch devices within the first feedback path, whereby upon actuation of the first plurality of switches, the first switched capacitor generates first ramp waveforms during first alternate clock periods of the clock signal. The circuit may also include a second switched capacitor device within a second feedback path of the operational amplifier, and a second plurality of switch devices within the second feedback path, whereby upon actuation of the second plurality of switches, the second switched capacitor generates second ramp waveforms during second alternate clock periods of the clock signal. The first alternate clock periods of the clock are followed by an adjacent one of the second alternate clock periods of the clock.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.

Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.

Abstract: A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.

Abstract: A voltage buffer having a fist transistor, a second transistor, a third transistor and a voltage detector is provided. A first terminal of the first transistor is coupled to a first reference voltage. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a control terminal of the second transistor is coupled to an input voltage, and a second terminal of the second transistor is coupled to an output voltage. A first terminal of the third transistor is coupled to a second terminal of the second transistor. A second terminal of the third transistor is coupled to a second reference voltage. The voltage detector detects a voltage of the second terminal of the first transistor to generate a detection result and outputs the detection result to a bulk terminal of the second transistor.

Abstract: A system comprises a first component operable in a plurality of modes coupled to a second component via an isolation circuit. The isolation circuit comprises a first diode coupled between a power supply of the first component and an output of the isolation circuit. The output of the isolation circuit is coupled to the second component. The isolation circuit also comprises a first transistor the base of which is coupled to an output of the first component and one of the collector and emitter of which is coupled to the output of the isolation circuit. In a low power mode of the first component, parasitic supply from the output of the isolation circuit is blocked from the power supply of the first component and from the output of the first component by the first transistor and the first diode.

Abstract: Disclosed herein is a power on reset (POR) circuit, including: a current mirror circuit adjusting ratio of current flowing in a circuit according to voltage supplied from power; an inverter driven according to output of the current mirror circuit to output a POR signal; a brown out detection (BOD) comparator electrically connected to the current mirror circuit and comparing the voltage supplied from the power with reference voltage to output a corresponding voltage signal according to the comparison result; a BOD controlling switch driven when the output of the BOD comparator is zero voltage (0V) to again operate a POR; and a current controlling switch installed in the current mirror circuit and driven when the output of the BOD comparator is zero voltage (0V) to control and supply current of the POR.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract: In a gate drive circuit including stages which are cascaded and which output gate signals each of the stages includes a first node, an output part, a first holding part and a second holding part. A voltage of the first node is converted to a high voltage in response to one of a vertical start signal and a carry signal of one of previous stages. The output part outputs a first clock signal as a gate signal through an output terminal in response to the high voltage of the first node. The first holding part applies a first low voltage to the output terminal, in response to a gate signal output from at least one of following stages. The second holding part applies a second low voltage, which is less than the first low voltage, to the first node in response to a gate signal output from at least one stage among following stages.

Abstract: A delay-locked loop (DLL) involves a pulse generating circuit that generates first and second pulses from an input clock signal. The second pulse is generated one clock signal period later than the first pulse. The first pulse is supplied to the input of a delay line. An edge of a delayed version of the first pulse as output from the delay line is phase-aligned with respect to a corresponding edge of the undelayed second pulse such that the DLL locks. The sending of pulses through the delay line of the DLL rather than clock signals having more edges per unit time helps reduce DLL aliasing problems and reduces the amount of switching in the delay line, thereby reducing power. consumption. A compact segmented delay line construction allows an input signal of arbitrary wave shape to be delayed by a fraction of the clock signal period.

Abstract: A slew rate regulation circuit varies a slew rate of a waveform of a voltage outputted to a DC motor through a N-channel MOSFET. The slew rate regulation circuit lowers a peak level by dispersing frequency components of switching noise, which develops in a frequency range higher than a frequency range determined by a carrier frequency.

Abstract: In a driver apparatus for driving a voltage-controlled switching element, an absolute value of a voltage difference between a voltage at a reference terminal that is one of terminals of a current path of the switching element and a voltage at the switching control terminal of the switching element is clamped at a clamping voltage greater than a threshold voltage. A voltage greater than the threshold voltage applied to the switching control terminal allows the switching element to be turned on. When the current flowing through the switching element becomes equal to or greater than a clamp threshold after the switching element transitions from an off-state to an on-state, a voltage-drop-rate at which the absolute value is decreased to the clamping voltage is decreased.

Abstract: Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.

Abstract: A double-swing clock generator includes a first double-swing clock generation circuit and a second double-swing clock generation circuit. The first double-swing clock generation circuit is used for receiving a first voltage, a second voltage, a first clock, an inverse first clock, and a third voltage, and outputting a first double-swing clock. The second double-swing clock generation circuit is used for receiving a fourth voltage, the second voltage, the first clock, the inverse first clock, and the third voltage, and outputting a second double-swing clock.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.