Abstract: The present disclosure relates generally to power-on-reset (POR) devices for activation of a circuit block powered by a battery. The POR devices activate a circuit block when a battery voltage level of a battery voltage generated by the battery is above a dead battery condition voltage level. So that the circuit block is activated after the battery voltage level of the battery voltage has reached the dead battery condition voltage level, the POR device includes a trigger circuit. The trigger circuit is operable to receive the battery voltage and is configured to generate a trigger signal in response to the battery voltage level being charged above a trigger voltage level, which is equal to or greater than the dead battery condition voltage level. The POR circuit is also operable to generate a POR signal in an activation state and activate the circuit block.

Abstract: A frequency multiplier includes: a multiphase signal generator configured to generate multiphase signals in response to a source signal; a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and a synthesizer configured to generate a frequency multiplication signal in response to edges of the pulse signals. Each of the plurality of pulse signals is generated in response to a corresponding multiphase signal, and the frequency multiplication signal is obtained by multiplying a frequency of the source signal.

Abstract: A level shifter includes a signal receiving module, including at least one signal receiving end for receiving at least one input signal and being conducted or non-conducted according to the input signal; a level adjusting module, configured to generate the adjusted output signal according to the input signal, wherein the level adjusting module includes a first connection end and a second connection end, the second connection end is coupled to the signal receiving module; and a switch module, including a first end coupling to the first connection end and a second end coupling to the second connection end. If the switch module is conducted, an current path is formed between the first connection end, the second connection end and the signal receiving module through the switch module. If the switch module is not conducted, current is blocked from flowing from the first connection end to the second connection end.

Abstract: The present subject matter discusses, among other things, apparatus and methods for a delay line. In an example, a delay device can include a first node, a plurality of variable capacitor circuits configured to receive a capacitance set point voltage, a current source, a plurality of switches configured to selectively couple a respective variable capacitor of the plurality of variable capacitors to the first node, an input switch configured to receive an input signal and to couple and decouple the current source to the first node responsive to a state of the input signal, and a comparator configured to receive a reference voltage, to receive a voltage from the first node, and to provide an binary output indicative of a comparison between the reference voltage and the voltage from the first node, wherein the binary output is a delayed representation of the input signal.

Abstract: A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.

Abstract: According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Abstract: The voltage level shifter includes a first voltage shift circuit, a second voltage shift circuit, a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit. The first voltage shift circuit receives a first input voltage, and the second voltage shift circuit receives a second voltage shift circuit. When the first voltage is high level voltage, a second output voltage and a first voltage are transformed to a ground voltage so as to open the second switch circuit and the fourth switch circuit, and then the first output voltage is transited to a system voltage. When the second voltage is high level voltage, a first output voltage and a second voltage are transited to a ground voltage so as to open the first switch circuit and the third switch circuit, and then the second output voltage is transited to the system voltage.

Abstract: The invention provides a voltage to current converter that contains an diode-connected NMOS transistor, a diode-connected PMOS transistor, and a voltage-controlled signal input circuit. The source of the NMOS transistor and the drain of the PMOS transistor are connected together and connected to the voltage-controlled signal input circuit in series. The invention is implemented and tested in the integrated circuit. When an input voltage signal is inputted, a current of the PMOS transistor is substantially linearly proportional to the input voltage signal.

Abstract: A frequency converter includes a comparator, an error computation unit and a calibration unit. The comparator receives a reference voltage signal and a triangle wave signal, and outputs a switching signal. The switching signal is fed back to the error computation unit to calculate an error signal by computing the reference signal and the switching signal. The calibration unit calibrates the triangle wave signal or the reference voltage signal according to the error signal.

Abstract: Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during each feedback cycle, thereby making it possible to achieve a phase lock faster and more efficiently. In some embodiments, such adaptive functionality can be incorporated into existing circuits with minimal impact.

Abstract: A drive circuit is provided for a target switching element and opens/closes a current path by controlling an absolute value of a potential difference between one end of the current path and an opening/closing control terminal. The drive circuit includes an integrated circuit connected to the control terminal. The integrated circuit includes an absolute value control circuit controlling the absolute value of the potential difference when the switching element is in an off-state, a stabilization circuit stabilizing the potential difference at a value for maintaining the switching element in an off-state when the switching element is in an off-state, a selection circuit selecting one of control of the absolute value of the potential difference by the control circuit and stabilization of the potential difference by the stabilization circuit, and an on-state terminal connected to the control circuit and the control terminal. The on-state terminal is connected to the stabilization circuit.

Abstract: A peripheral device and a method for programming the read/writeable memory of the RFID circuitry by communications between either RF antenna or bus communications port controller interface or both. In the peripheral device, an EEPROM, bus communications controller interface, NFC interface, antenna, and logic controller operate to receive and transmit configuration and calibration data between a wireless personal area network circuit and an external wireless personal area network enabled device. The dual interfaced EEPROM is operable to share or partition its EEPROM between an NFC interface and a bus communications controller.

Abstract: Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength of an output driver and configuring the pre-driver based on the determined output driver strength.

Abstract: An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.

Abstract: An integrated circuit includes a clock circuit that may be used to provide clock signals to multiple input-output circuits. The integrated circuit may also include different clock structures. As an example, one of the clock structures may have multiple clock paths of substantially equal lengths while another clock structure may have a fly-by clock path. The multiple clock paths may be used to convey a subset of the clock signals to the input-output circuits. Similarly, the fly-by clock path may be used to transmit a second subset of the clock signals to the input-output circuits.

Abstract: A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.

Abstract: An interface circuit for signal transmission includes an amplifying circuit, a de-skew circuit and a latching unit. The amplifying circuit receives an input clock signal and outputs an output clock signal after amplifying the input clock signal. The de-skew circuit receives the output clock signal and outputs a de-skew clock signal as a trigger signal after removing a skew time of the output clock signal. The latching unit includes multiple sampling circuits, respectively receives multiple inputting data signals. The sampling circuits are controlled by the trigger signal to sample the inputting data signals and output multiple outputting data signals. The voltage amplitudes of the outputting data signals are larger than the voltage amplitudes of the inputting data signals and satisfy a required voltage amplitude by a subsequent circuit.

Abstract: A driver includes a converter section 2 which includes a switching element Q1 and which is configured to output a desired DC voltage by switching the switching element Q1, a control section 1 configured to control the switching operation of the switching element Q1, capacitors C1A, C1B charged by the output of the converter section 2, turn-on circuits 31A, 31B configured to supply gates of a bidirectional switch element 4 using electric charges stored in the capacitors CIA, C1B with drive powers to turn-on the bidirectional switch element 4, and turn-off circuits 32A, 32B configured to discharge the capacitors CIA, C1B to turn-off the bidirectional switch element 4 in response to the halt of the switching operation of the switching element Q1 by the control section 1.

Abstract: A voltage to frequency conversion system may be used in association with clock related applications such as a closed loop oscillator. The voltage to frequency conversion system includes independent current sources that are synchronously operated to generate substantially the same respective output currents under varying temperature and supply voltage conditions. One of the current sources is used to generate a reference voltage, and the other of the current sources is used to charge a capacitor in a predetermined ramp. The capacitor may be selectively charged and discharged based on a frequency of an input signal, and an average of the variable charge voltage of the capacitor may be compared to the reference voltage to generate an analog output signal indicative of frequency.

Abstract: Disclosed herein are a tunable capacitance control circuit and a tunable capacitance control method. The tunable capacitance control method is a tunable capacitance control method by a tunable capacitance control circuit including an MIM capacitor, a plurality of FET switches, and a control unit, wherein the control unit outputs control signals allowing only one of the plurality of (n) FET switches to be switched on and the remaining (n?1) FET switches to be switched off to the plurality of FET switches, thereby obtaining a desired tunable capacitance value.