Patents Examined by Dao H. Nguyen
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Patent number: 11855151Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.Type: GrantFiled: June 21, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Sheng Chen, Cheng-Hsien Wu, Chih Chieh Yeh, Yee-Chia Yeo
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Patent number: 11848328Abstract: Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second STI regions arranged in a first direction, a first diffusion region having a first conductivity type surrounded by the first STI region, a second diffusion region having a second conductivity type surrounded by the second STI region, and a third diffusion region extending in a second direction such that the third diffusion region is arranged between the first and second STI regions; a first gate electrode including a first polycrystalline silicon film covering a part of the first diffusion region to form a P-channel MOS transistor; a second gate electrode including a second polycrystalline silicon film covering a part of the second diffusion region to form an N-channel MOS transistor; and a third polycrystalline silicon film extending in the second direction such that the third polycrystalline silicon film covers the third diffusion region.Type: GrantFiled: December 7, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Ryota Suzuki, Makoto Sato, Hirokazu Matsumoto, Kyoka Egami
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Patent number: 11848374Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.Type: GrantFiled: January 13, 2022Date of Patent: December 19, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Shesh Mani Pandey, Jagar Singh, Judson Holt
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Patent number: 11843050Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.Type: GrantFiled: August 9, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Pei-Yu Wang, Sai-Hooi Yeong
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Patent number: 11837566Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.Type: GrantFiled: November 23, 2021Date of Patent: December 5, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
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Patent number: 11837663Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.Type: GrantFiled: August 2, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
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Patent number: 11830950Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.Type: GrantFiled: June 14, 2021Date of Patent: November 28, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi
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Patent number: 11830820Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.Type: GrantFiled: December 16, 2021Date of Patent: November 28, 2023Assignee: MEDIATEK INC.Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
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Patent number: 11830927Abstract: A method includes: forming a dummy gate dielectric layer over a channel region of a fin structure; forming a dummy gate over the dummy gate dielectric layer; removing the dummy gate and a first portion of the dummy gate dielectric layer to expose the channel region of the fin structure; removing a first nanowire of the fin structure above a second nanowire of the fin structure to remain the second nanowire of the fin structure; forming an interfacial layer surrounding the second nanowire; forming a material layer comprising dopants over the interfacial layer; and performing an annealing process to drive the dopants of the material layer into the interfacial layer, thereby forming a doped interfacial layer surrounding the second nanowire.Type: GrantFiled: January 13, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Cheng-Hsien Wu
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Patent number: 11830817Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.Type: GrantFiled: October 30, 2020Date of Patent: November 28, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Rahul Agarwal, Raja Swaminathan, Michael S. Alfano, Gabriel H. Loh, Alan D. Smith, Gabriel Wong, Michael Mantor
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Patent number: 11810875Abstract: A packaged integrated circuit (IC) includes an IC die having first and second external contacts and a package substrate. The IC die is attached to the package substrate which includes a balun in a first metal layer. The balun is connected to the first and second external contacts of the IC die and to a first external contact of the package substrate. The first and second external contacts of the IC die communicate a differential signal with the package substrate, and the first external contact of the package substrate communicates a single-ended signal corresponding to the differential signal. Alternatively, the balun is connected to an external contact of the IC die and to first and second external contacts of the package substrate, in which the external contact of the IC die communicates a single-ended signal and the first and second external contacts of the package substrate communicate a differential signal.Type: GrantFiled: April 9, 2021Date of Patent: November 7, 2023Assignee: NXP B.V.Inventors: Waqas Hassan Syed, Cicero Silveira Vaucher, Antonius Johannes Matheus de Graauw
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Patent number: 11799017Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.Type: GrantFiled: March 22, 2022Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
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Patent number: 11793017Abstract: A display device includes a display panel, a cover member disposed on the display panel, and an adhesive layer disposed between the display panel and the cover member. The adhesive layer has a first surface facing the cover member and a second surface facing the display panel, and includes a first area and a second area disposed at positions different from each other in a first direction from the first surface toward the second surface. A modulus of the first area is different from a modulus of the second area.Type: GrantFiled: June 8, 2022Date of Patent: October 17, 2023Assignee: Samsung Display Co., Ltd.Inventor: Kukbin Lim
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Patent number: 11791315Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors.Type: GrantFiled: November 5, 2021Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, Owen R. Fay, Eiichi Nakano
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Patent number: 11784218Abstract: A semiconductor device includes a gate disposed over a substrate. A source/drain is disposed in the substrate. A conductive contact is disposed over the source/drain. An air spacer is disposed between the gate and the conductive contact. A first component is disposed over the gate. A second component is disposed over the air spacer. The second component is different from the first component.Type: GrantFiled: January 8, 2021Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen
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Patent number: 11764248Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes an image sensor disposed within a first substrate. A first band-pass filter and a second band-pass filter are disposed on the first substrate. A dielectric structure is disposed on the first substrate. The dielectric structure is laterally between the first band-pass filter and the second band-pass filter and laterally abuts the first band-pass filter and the second band-pass filter.Type: GrantFiled: October 21, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
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Patent number: 11764311Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.Type: GrantFiled: September 28, 2021Date of Patent: September 19, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee
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Patent number: 11756953Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.Type: GrantFiled: June 22, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Hao Chiang, Wun-Jie Lin, Jam-Wem Lee
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Patent number: 11749729Abstract: A semiconductor device includes a gate structure, source/drain (S/D) elements, a first metallization contact and a second metallization contact. The S/D elements are respectively located at two different sides of the gate structure. The first metallization contact is located at and in contact with a first side of each of the S/D elements. The second metallization contact is located at and in contact with a second side of each of the S/D elements, where the semiconductor device is configured to receive a power signal through the second metallization contact. The first side is opposite to the second side along a stacking direction of the gate structure and the S/D elements, and the first side is closer to the gate structure than the second side is.Type: GrantFiled: March 31, 2021Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ming-Fa Chen
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Patent number: 11742394Abstract: Provided are a semiconductor substrate and a transistor. The semiconductor substrate includes a base, an insulating layer, a semiconductor layer, a wide bandgap diffusion buffer layer and a nucleation layer. The insulating layer is disposed on the base. The semiconductor layer is disposed on the insulating layer. The wide bandgap diffusion buffer layer is disposed on the semiconductor layer, wherein the bandgap of the wide bandgap buffer diffusion layer is higher than 2.5 eV. The nucleation layer is disposed on the wide bandgap diffusion buffer layer, wherein the nucleation layer includes an aluminum-containing layer.Type: GrantFiled: December 8, 2021Date of Patent: August 29, 2023Assignee: Industrial Technology Research InstituteInventor: Hsueh-Hsing Liu