Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

Abstract: Provided are a solid-state image-capturing device, a semiconductor apparatus, an electronic apparatus, and a manufacturing method that enable improvement in reliability of through electrodes and increase in density of through electrodes. A common opening portion is formed including a through electrode formation region that is a region in which the plurality of through electrodes electrically connected respectively to a plurality of electrode pads provided on a joint surface side from a device formation surface of a semiconductor substrate is formed. A plurality of through portions is formed so as to penetrate to the plurality of respective electrode pads in the common opening portion, and wiring is formed along the common opening portion and the through portions from the electrode pads to the device formation surface corresponding to the respective through electrodes. The present technology can be applied to a layer-type solid-state image-capturing device, for example.

Abstract: A substrate, a manufacturing method of a substrate and an electronic device are provided. The substrate includes a working region, a non-working region surrounding the working region, a base substrate, a peripheral circuit and a common electrode lead both in the non-working region and on the substrate; the common electrode lead is located on a side of the peripheral circuit close to the working region.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.

Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.

Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.

Abstract: The present technology relates to a semiconductor device, an imaging device, and a manufacturing apparatus, capable of providing a semiconductor substrate maintaining and improving insulating performance. A through hole that penetrates the semiconductor substrate, an electrode at the center of the through hole, and a space around the electrode are included. The through hole also penetrates an insulating film formed on the semiconductor substrate. A barrier metal is further included around the electrode. An insulating film is further included in the semiconductor substrate and the space. The semiconductor device has a multilayer structure, and the electrode connects wirings formed in different layers to each other. The present technology can be applied to, for example, an image sensor in which a logic circuit and a sensor circuit are laminated.

Abstract: A resistive random-access memory (ReRAM) includes a hybrid memory cell. The hybrid memory cell includes: (a) a left resistance-switching device comprising a first terminal and a second terminal, (b) a right resistance-switching device comprising a first terminal and a second terminal, wherein the first terminal of the right resistance-switching device is connected to the first terminal of the left-resistive switching device at an internal node, and (c) a transistor comprising a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the transistor is connected to the left resistance-switching device and the right resistance-switching device at the internal node.

Abstract: A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

Abstract: A sensing module, a semiconductor device package and a method of manufacturing the same are provided. The sensing module includes a sensing device, a first protection film and a second protection film. The sensing device has an active surface and a sensing region disposed adjacent to the active surface of the sensing device. The first protection film is disposed on the active surface of the sensing device and fully covers the sensing region. The second protection film is in contact with the first protection film and the active surface of the sensing device.

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.

Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

Abstract: A display panel includes: an upper display substrate including a plurality of pixel areas arranged in each of a plurality of pixel columns and a light blocking area disposed adjacent to the pixel areas; and a lower display substrate including a plurality of display elements respectively overlapping the pixel areas, wherein the upper display substrate includes: a base substrate; a color filter layer disposed on the base substrate; and a light control layer disposed on the color filter layer and including transmission portions respectively at least partially overlapping first pixel areas arranged in a first one of the pixel columns and first conversion portions respectively at least partially overlapping second pixel areas arranged in a second one of the pixel columns, wherein the light blocking area includes a first light blocking area defined between the transmission portion and the first conversion portion, and a second light blocking area defined between the first conversion portions, and a first shortest d

Abstract: A method of fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer over a semiconductor substrate and forming first and second via contacts in the first dielectric layer and extending below a bottom surface of the first dielectric layer. The method also includes etching back the first dielectric layer to expose upper portions of the first and second via contacts. The method further includes depositing an etch stop layer conformally on the upper portions of the first and second via contacts and on the first dielectric layer. In addition, the method includes depositing a second dielectric layer on the etch stop layer and forming first and second metal lines in the second dielectric layer to be electrically connected to the first via contact and the second via contact, respectively.

Abstract: Provided is a semiconductor device including a semiconductor layer in which a plurality of pixels each including a photoelectric converter is provided, and an interconnection structure arranged over the semiconductor layer. The plurality of pixels includes a first light-receiving pixel and a second light-receiving pixel, the interconnection structure includes a first insulating film made of a first insulating material, a first insulating member arranged in association with the first light-receiving pixel and made of a second insulating material having a larger hydrogen content than the first insulating material, and a second insulating member arranged in association with the second light-receiving pixel and made of the second insulating material, and a volume of the first insulating member is larger than a volume of the second insulating member.