Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Abstract: A charge-modulation element encompasses a p-type photoelectric-conversion layer, a n-type surface-buried region buried in an upper portion of the photoelectric-conversion layer configured to implement a photodiode with the photoelectric-conversion layer, a n-type modulation region buried in another part of the upper portion of the photoelectric-conversion layer configured to implement a part of the photodiode with the photoelectric-conversion layer, potential-control regions assigned in one of divided areas, n-type charge-accumulation regions configured to accumulate signal charges generated in the photodiode. Potentials in the modulation region and the surface-buried region are controlled by route-select signals applied to the potential-control regions so as to select one of the charge-transport routes, which transfers the signal charges toward one of the charge-accumulation regions.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a gate spacer adjacent to the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed over the substrate and adjacent to the gate electrode layer. An air gap is formed between the gate spacer and the source/drain contact structure, and the air gap is in direct contact with the gate spacer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

Abstract: The present technology relates to a semiconductor device and an electronic apparatus that are capable of improving the characteristics of a semiconductor device or an electronic apparatus that includes a pixel having a metallic filter and a pixel not having the metallic filter. A semiconductor device includes: a pixel unit in which a first pixel including a metallic filter and a second pixel not including the metallic filter are disposed adjacent to each other; and a reflected light reduction unit that reduces reflected light on a sidewall of the metallic filter at a boundary portion between the first pixel and the second pixel. The present technology can be applied to an image sensor that includes a narrowband pixel including a plasmon filter and a normal pixel including a color filter, for example.

Abstract: A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.

Abstract: The present disclosure provides a semiconductor device with an air gap and a boron nitride cap for reducing capacitive coupling in a pattern-dense region and a method for preparing the semiconductor device. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a boron nitride layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the boron nitride layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

Abstract: A mother substrate for display substrates, a manufacture method thereof, a display substrate and a display device are provided. The mother substrate for display substrates includes multiple display element formation regions and a dividing line surrounding each display element formation region. A recess-protrusion structure is provided between the dividing line and the display element formation region, the recess-protrusion structure includes multiple recesses and protrusions which are arranged alternately, and extension directions of the recess and the protrusion are identical to an extension direction of the dividing line.

Abstract: A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.

Abstract: A sensor device including an interposer including a first via and a lower pad, the lower pad being on a bottom surface of the interposer; an image sensor chip on a top surface of the interposer, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including first wiring patterns and a second via, and the sensing chip including second wiring patterns; a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring patterns and at least one of the second wiring patterns; and a passivation layer on an inner surface of the conductive structure, wherein a side surface of the interposer is coplanar with a side surface of the image sensor chip.

Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

Abstract: An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

Abstract: The present application provides a method of bonding an integrated circuit chip to a display panel. The method includes forming a plurality of first bonding pads in a bonding region on a first side of the display panel; forming a plurality of vias extending through the display panel in the bonding region; subsequent to forming the plurality of vias, disposing an integrated circuit chip having a plurality of second bonding pads on a second side of the display panel substantially opposite to the first side, the plurality of second bonding pads being on a side of the integrated circuit chip proximal to the display panel; and electrically connecting the plurality of first bonding pads respectively with the plurality of second bonding pads by forming a plurality of connectors respectively in the plurality of vias.

Abstract: An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.