Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: A method of removing post-etch residues is provided. First, a substrate is provided. An isolation layer covers the substrate and a conductive layer is embedded in the isolation layer. A dielectric layer and a hard mask cover the isolation layer. Then, an etching process is performed, and a patterned hard mask is formed by etching the hard mask by ions or atoms. After that, a charge-removing process is performed by using a conductive solution to cleaning the patterned hard mask and the dielectric layer so as to remove the charges accumulated on the patterned hard mask and the dielectric layer during the etch process. Finally, the post-etch residues on the patterned hard mask and the dielectric layer is removed.

Abstract: Methods of fabricating a semiconductor device on and in a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, wherein the sacrificial mandrel has sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion. The upper portion of the sidewall spacers is removed. The sacrificial mandrel is removed and the semiconductor substrate is etched using the lower portion of the sidewall spacers as an etch mask.

Abstract: A method of preventing arcing during bevel edge etching a semiconductor substrate with a plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the plasma in the bevel etcher while evacuating the bevel etcher to a pressure of 3 to 100 Torr while maintaining RF voltage seen at the wafer at a low enough value to avoid arcing.

Abstract: A method of preparing a stepped structure in a multi-layer film stack on a substrate is described. The multi-layer film stack includes alternating layers of differing composition, wherein the alternating layers of differing composition include one or more layers of a first composition and one or more layers of a second composition. The method includes transferring a mask pattern to the one or more layers of the first composition to form a first layer pattern in the one or more layers of the first composition using a first etch process, trimming the mask pattern to expose another portion of the one or more layers of the first composition using a mask trim process, and following the trimming, transferring the first layer pattern to the one or more layers of the second composition using a second etch process.

Abstract: A production method of a suspension board with circuit includes the steps of forming, on a metal supporting board, an insulating layer formed with a first opening, forming a metal thin film on the insulating layer and on the metal supporting board exposed from the first opening, forming, on a surface of the metal thin film, a conductive layer having terminal portions forming, on the terminal portions, a metal plating layer by electrolytic plating using the metal supporting board as a lead, forming a second opening in a portion of the metal supporting board opposing the first opening, and partially etching the metal supporting board to form the suspension board with circuit and a support frame. In the step of forming the insulating layer, the first opening is formed in the insulating layer in which the supporting frame is formed.

Abstract: A method for producing a pattern in an aerogel disposed as a coating on a substrate comprises exposing the aerogel coating to the vapors of a hydrophobic silane compound, masking the aerogel coating with a shadow photomask and irradiating the aerogel coating with ultraviolet (UV) irradiation. The exposure to UV through the shadow mask creates a pattern of hydrophobic and hydrophilic regions in the aerogel coating. Etching away the hydrophilic regions of the aerogel coating, preferably with a 1 molar solution of sodium hydroxide, leaves the unwetted and unetched hydrophobic regions of the aerogel layer on the substrate, replicating the pattern of the photomask. The hydrophobic aerogel pattern can be further exposed to UV irradiation if desired, to create a hydrophilic aerogel pattern.

Abstract: The invention provides a plasma processing apparatus and a method for purging the apparatus, capable of preventing damage of components caused by pressure difference during purging operation of a vacuum reactor, and capable of preventing residual processing gas from remaining in the vacuum reactor. Inert gas is introduced through an inert gas feed port 233 on a side wall of a depressurized processing chamber (V1) 226 of a plasma processing apparatus, and the interior of the processing chamber (V1) 226 is brought to predetermined pressure by the inert gas, and thereafter, the inert gas is supplied to processing gas supply paths 213 and 216 (V2) communicated to a plurality of through holes 224 for introducing processing gas, so as to introduce the inert gas through the plurality of through holes 224 into the processing chamber (V1) 226.

Abstract: A method of imprinting a microstructure comprising: contacting a stamper comprising a pattern layer with the microstructure of the order of from micrometers to nanometers in one face of the pattern layer and a substrate supporting the pattern layer with an imprinting member having a deformable layer to which the microstructure is imprinted, wherein the pattern layer is supported on a round surface having a prescribed radius of curvature of the substrate, the center of the round surface protruding towards the rear face of the pattern layer; causing the deformable layer on the imprinting member; and separating the stamper from the cured deformable layer.

Abstract: Methods comprising providing a pre-patterned substrate having an array of thick walls, depositing a conforming layer on the pre-patterned substrate, etching the conforming layer from the top of the thick walls and the space between the walls, and etching the thick walls while leaving thin walls of conforming layer.

Abstract: Disclosed is a method for directly preparing cerium oxide powder in a solution phase by a) mixing a cerium precursor solution with a precipitant solution to cause a reaction; and b) performing oxidation treatment of the reacted solution, wherein at least one kind of pure organic solvent containing no water is used as a solvent for the cerium precursor solution as well as the precipitant solution to thereby prepare the cerium oxide powder, the particle size of which is adjusted to 50 nm to 3 ?m. Cerium oxide powder obtained from the method and CMP slurry comprising the cerium oxide powder as a polishing agent are also disclosed.

Abstract: Disclosed is an adjuvant for controlling polishing selectivity when polishing a cationically charged material simultaneously with an anionically charged material. CMP slurry comprising the adjuvant is also disclosed. The adjuvant comprises: (a) a polyelectrolyte that forms an adsorption layer on the cationically charged material in order to increase the polishing selectivity of the anionically charged material; (b) a basic material; and (c) a fluorine-based compound. when the adjuvant for controlling polishing selectivity of CMP slurry according to the present invention is applied to a CMP process, it is possible to increase the polishing selectivity of a silicon oxide layer, to obtain a uniform particle size of CMP slurry, to stabilize variations in viscosity under an external force and to minimize generation of microscratches during a polishing process.

Abstract: A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

Abstract: A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract: A method for chemical mechanical polishing of a substrate, comprising: providing a substrate, wherein the substrate comprises silicon dioxide; providing a chemical mechanical polishing composition, wherein the chemical mechanical polishing composition comprises: water, an abrasive; a diquaternary cation according to formula (I); and optionally a quaternary alkylammonium compound; providing a chemical mechanical polishing pad; creating dynamic contact at an interface between the chemical mechanical polishing pad and the substrate; and dispensing the chemical mechanical polishing composition onto the chemical mechanical polishing pad at or near the interface between the chemical mechanical polishing pad and the substrate; wherein the chemical mechanical polishing composition has a pH of 2 to 6; wherein the chemical mechanical polishing composition exhibits a silicon dioxide removal rate of at least 1,500 ?/min.

Abstract: Provided is a method of manufacturing a ceramic probe card. A ceramic laminated body having a plurality of ceramic green sheets and an interlayer circuit including a conductive via and a conductive line formed in the plurality of ceramic green sheets is prepared. Then, at least one probe pin structure connected to the interlayer circuit is formed by selectively removing the plurality of photosensitive ceramic sheets having a ceramic powder and a photosensitive organic component on the ceramic laminated body necessarily, and by filling a metal material in a region from which the plurality of photosensitive ceramic sheets have been removed. Then, a ceramic substrate having the at least one probe pin structure is provided by simultaneously firing the ceramic laminated body and the photosensitive ceramic sheets, and by removing the photosensitive ceramic sheets.

Abstract: A method for fabricating diamond nanopillars includes forming a diamond film on a substrate, depositing a metal mask layer on the diamond film, and etching the diamond film coated with the metal mask layer to form diamond nanopillars below the mask layer. The method may also comprise forming diamond nuclei on the substrate prior to forming the diamond film. Typically, a semiconductor substrate, an insulating substrate, a metal substrate, or an alloy substrate is used.

Abstract: The invention provides methods of polishing a noble metal-containing substrate with one of two chemical-mechanical polishing compositions. The first chemical-mechanical polishing composition comprises (a) an abrasive comprising ?-alumina, (b) about 0.05 to about 50 mmol/kg of ions of calcium, strontium, barium, or mixtures thereof, and (c) a liquid carrier comprising water. The second chemical-mechanical polishing composition comprises (a) an abrasive selected from the group consisting of ?-alumina, ?-alumina, ?-alumina, ?-alumina, diamond, boron carbide, silicon carbide, tungsten carbide, titanium nitride, and mixtures thereof, (b) about 0.05 to about 3.5 mmol/kg of ions of calcium, strontium, barium, magnesium, zinc, or mixtures thereof, and (c) a liquid carrier comprising water.

Abstract: Native oxide film on a semiconductor silicon wafer(s) is dry etched at a temperature of 50° C. or less. Hydrogen treatment is then carried out a temperature of 100° C. or more to bond the dangling bonds with hydrogen. A jig 9 that has been used is again used for loading new semiconductor silicon wafer(s) 10. The wafer(s) on the jig 9 is subjected to removal of a native oxide film and then hydrogen bonding. The resultant heat remains in jig and makes it difficult to maintain the wafers to temperature appropriate to removal of a native oxide film. After treatment of hydrogen bonding, inert gas having temperature of from 0 to ?30° C. is injected into reaction vessel 5 and/or treatment preparing vessel 21, in which a native oxide film has been removed.