Abstract: The invention is an alphabetic keyboard arrangement for convenient and fast typing--for instructional, research or data entry purposes--the phonetic data or phonetic transcriptions of Mandarin Chinese in the pinyin romanization. Its distinguishing features are the following: (1) the keys bearing the letters A, I, O and U are so placed that each is usually struck by a different finger; (2) the keys bearing the letters A, I, O, U, N and G, as these letters stand for the most frequently appearing syllabic final speech sounds, are placed in the row of keys on which the typist's fingers usually rest; (3) the keys bearing the letters A, E, I, U and H are so placed that each is usually struck by the index finger or middle finger of either hand; (4) the keys bearing the syllabic tone quality symbols are in the central are of the keyboard.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.

Abstract: A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.

Abstract: An apparatus and method for loading BIOS stored on a direct access storage device into a personal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, and at least one direct access storage device. The first portion of BIOS initializes the system and the direct access storage device to read in a master boot record into the system from the direct access storage device. The master boot record includes a data segment and an executable code segment. The first BIOS portion vectors the system processor to execute the executable code segment of the master boot record. The executable code segment loads in the remaining BIOS portion from the direct access storage device into random access memory.

Abstract: A database index file is maintained by a computer system having primary random access memory and secondary memory. A record for each item added to the database is stored in a sequential file in secondary memory (disk storage) and an indexed pointer to the new record is stored in a small B-tree stored in primary random access memory. The full index file for the database is a second, large B-tree stored in secondary memory. Leaf-nodes of the full index file are stored in indexed order. Periodically, a portion of the memory resident small B-tree is merged with a corresponding portion of the large B-tree by selecting a range of index values and retrieving from secondary memory all indexed pointers in the selected range of index values. The indexed pointers in the first B-tree in the selected range of index values are merged into the retrieved records, the resulting merged set of indexed pointers are stored in secondary memory in indexed order in a contiguous area of secondary memory.

Abstract: Apparatus and method for increasing efficiency of command execution from a host processor over an SCSI bus. Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine. Additional protocol functions are implemented in a foreground state machine. When the host processor issues a command for access to the SCSI bus, the background state machine can be programmed before the foreground machine completes the protocol function for a previous command. Thus, the background state machine is ready to arbitrate for access to the bus at the very next bus free condition.

Abstract: A method of memory access for sharing a memory between multiple processors. The memory comprises a plurality of sections and each section is connected to each processor by a memory path. Each section includes a plurality of subsections and each subsection includes a plurality of banks which includes a plurality of individually addressable memory locations. Memory references attempting to access the individually addressable memory locations are generated by the processors. Subsection conflicts between the memory references generated by a plurality of ports of each processor are resolved so that only one of the memory references from each processor is allowed to access one of the plurality of subsections at a time. Section conflicts between the memory references generated by the plurality of ports of each processor are resolved so that only one of the plurality of ports of each processor connects by the memory path for each processor to one of the plurality of the sections at a time.

Abstract: A table memory is provided for selecting types of files to be updated in accordance with identification codes designating types of transactions. When a transaction occurs, the corresponding transaction record and the identification code indicating the type of transaction are generated. Data from the table memory is retrieved in accordance with the identification code to select all the files to be updated. The selected files are sequentially updated in accordance with the transaction record.

Abstract: System and method of designing and developing table translation software in which an operation is performed on input data provided in the form of tables, and data resulting from the operation is also provided in the form of tables. The system includes an item input section for inputting items representative of attributes of data, a relation input section for inputting inter-item relations for the inputted items, an item and relation managing section for holding and supplying the inputted items and inter-item relations thereof, and a relation indicating section for indicating the items and the inter-item relations thereof held by the item and relation managing section. Software is designed and developed with the functions of the software being handled as translation processes of the tables.

Abstract: In the method and apparatus of the present invention a file to be added to the database is given a unique name that is dependent upon the contents of the file such that, when the contents of the source file changes, the name of the database component file to be added to the database also changes. Conversely, if two files of the same name have the same information contained therein, the same file name will be generated and the duplication of information in the database is prevented by providing a simple test that checks for the existence of the name of the database file before the generation and addition of the new file to the database. If the file name exists in the database, information is already contained in the database and the file is not generated and added to the database information. Preferably the name of the file is generated by computing a hash value from the contents of the file concatenating the hash value to the name of the source file.

Abstract: An attribute-based automated classification and retrieval system for group technology applications using a codeless classification system in which hierarchical classification structures are stored in a classification attribute file and in which searches can be performed at any level in the classification structure. The relationship between entities and classification attributes are kept in an item classification parameters file along with the parameter values associated with each entity-attribute pair. Queries on the data stored in the classification attribute file and item classification parameters file are stored alternately in a plurality of query results files as successive queries are used to narrow the scope of a search.

Abstract: An improved database management system (DBMS) stores, retrieves and manipulates directed graph data structures in a relational database. Each directed graph data structure contains one or more records of data which are interconnected by pointers. Data is stored in the database in the form of two dimensional tables, also known as flat files. The improved DBMS defines a schema for each table in the database. The schema defines the name and data type of each column in a database table. In tables used to store directed graph data structures, at least one column will be defined as having a reference data type. Non-empty entries in that column are pointers to rows in a specified table. Directed graph data structures are stored in specified tables by storing each record of the directed graph in a distinct row of one of the specified tables, with references corresponding to interconnections between records being stored in reference data type columns.

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus.

Abstract: A computer program to be compiled is optimized prior to carrying out the final compilation. Subgraphs within the program are identified and examined for optimization beginning with the entire program as the largest subgraph. The number of entities in each subgraph which are relevant to each dimension of arrays used to represent data flow equations is determined. Next, the amount of memory required to contain the arrays is determined. If that memory requirement is within a predefined memory usage limit for the compilation, then a specified procedure of the compilation process is applied. If the memory requirement to contain the arrays exceeds the predefined memory usage limit for the compilation, the process is repeated for successively smaller subgraphs within the program in an attempt to find a subgraph to which the memory limits allow application of the specified procedure.

Abstract: Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor.

Abstract: Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor is described. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them, and the apparatus includes data transfer circuitry connected between the processors for enabling the data to be transferred, a program instruction decoder associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring, and routing circuitry for carrying the data transfer commands from the first processor to the program instruction decoder for decoding to provide signals to the data transfer circuitry to effect a transfer of data.

Abstract: A computer system for executing application programs with limited available main memory capacity includes a main memory management system. The architecture of the stub vectors of a swappable code object and the protocol for referencing the stubs in active call frames reduces the overhead time of code object swapping. The stub vectors for a swappable code object are clustered together in memory; and each cluster comprises at least one entry stub and a return stub. A return stub vector is referenced in an active call frame only when its associated code object is not resident in main memory or when the code object has been placed on probation in contemplation of moving the object out of main memory. A linked list of resident code objects is employed in the selection of objects to be removed from main memory. A number of the least recently used code objects are put on probation in anticipation of the need to swap code between main memory and bulk memory.

Abstract: The Avionics Program Expert (APEX) is an automatic code generation tool for the Ada programming language (MIL-STD 1815A). It provides the programmer using APEX with the ability to quickly create a graphical representation of his initial program design. The graphical representation used by APEX is akin to a flowchart, but the interactive capabilities of the tool make design creation much faster and more efficient. Once the programmer has created his complete (or even partial) representation of a program, Ada code can then be generated with (from) APEX. The APEX program representation provides the user with three different, yet consistent, views of his program. The first view allows the programmer to lay out his initial Ada package specifications; this view is called the APEX view. A second view allows the programmer to create and manipulate complex data structures and define local variables; this view is the Data Structure view.

Abstract: In a multitasking, multiuser computer system, a server process temporarily impersonates the characteristics of a client process when the client process preforms a remote procedure call on the server process. Each process has an identifier list with a plurality of identifiers that characterize the process. The server process generates a new identifier list which is either the same as the client process's list, or is the union of the server's and the client's lists. Each object in the system can have an access control list which defines the identifiers that a process must have in order to access the object. The operation system has access checking software for enabling a selected process access to a specified object when the identifers for the process match the list of identifiers in the access control list of the specified object. The server can therefore access all objects accessible to the client while the server is working for the client.

Abstract: A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction also is used to initialize the DMA byte counter. During a subsequent write transaction, DMA pointer registers are initialized with appropriate starting addresses. The controller then transmits a DMA start code and the system resource responds by transmitting an acknowledge code. At that time, DMA data is transmitted between the controller and the system resource via the switching logic.