Patents Examined by David L. Clark
  • Patent number: 5109480
    Abstract: A color graphic display system is disclosed including a drawing process for displaying video data on a display device wherein the data is particularly intended to include superposed pictures. The processor includes an arithmetical operation unit which will allow addition/subtraction of video data items representative of the picture elements to be superposed. Further included is a condition setting circuit for selectively inhibiting carrys or borrows during the arithmetical operations between selected bits of a data word representative of an element such as a pixel of the picture being displayed. More particularly, where a video data item is comprised of sets of bits each set of which is representative of a main color of the pixel, and when two video data items are added or subtracted, the carrys that may normally occur between the different sets are inhibited to avoid interference between the sets that may affect the color of the resulting video data item.
    Type: Grant
    Filed: December 12, 1989
    Date of Patent: April 28, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Sone, Jun Sato
  • Patent number: 5101364
    Abstract: A video editing and viewing facility and method allows representation and arbitrary association of discrete image segments, both to create final compositions and to permit selective viewing of related segments. The user represents an image segment by a single frame or series of frames that acts as a mnemonic reference. Information regarding image segments is retained in data structures that facilitate relational designations thereamong and sorting of image segments. Display of a segment may be interrupted and a new segment initiated on command, and provision maintained for return to the original segment when display of the new segment is completed.
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: March 31, 1992
    Assignee: Massachusetts Institute of Technology
    Inventors: Glorianna Davenport, Hans P. Brondmo
  • Patent number: 5095446
    Abstract: Data to be sent to a frame buffer memory keeping output data in a bit map form is subdivided into square blocks. The words arranged in the row direction are rotated in a column direction by a bit each time the row address is increased. The rotation amount is attained by adding the row and column addresses associated with the square block.
    Type: Grant
    Filed: March 11, 1988
    Date of Patent: March 10, 1992
    Assignee: Hitachi, Ltd.
    Inventor: Kunio Jingu
  • Patent number: 5086482
    Abstract: An image processing method for generating a convex hull of a configuration in a digital image. Top points of the convex hull are selected. A reference line connecting the top points is defined. For each area between two adjacent top points, continuous pixels are selected from one top point toward the other so that each pixel is the nearest to the referfence line as well as between the reference line and a contour of the configuration. Distances from pixels to the reference line are calculated from chain codes.
    Type: Grant
    Filed: January 25, 1989
    Date of Patent: February 4, 1992
    Assignee: Ezel, Inc.
    Inventor: Ryohei Kumagai
  • Patent number: 5079724
    Abstract: A word processing apparatus with a function of an image-format control includes an image data storage for storing image data imputted in a certain format, an reading unit for reading the image data from the image data storage, a display device for displaying a region on a screen, a magnification/reduction control unit for calculating a virtual print size of the read image data, comparing the virtual print size with the size of the region, and magnifying or reducing the size of the read image data when those compared sizes are not equal so as to put the image within the region.
    Type: Grant
    Filed: September 26, 1989
    Date of Patent: January 7, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tatsuya Shiraki, Makoto Kado
  • Patent number: 5068808
    Abstract: An apparatus and process for the flexible and rapid manipulation of multidimensional data is disclosed. Coordinates ae transformed by the use of a plurality of transform memories, each being addressable by a coordinate of an n-tuple. Each member provides an intermediate value that when added to others provides a transformed coordinate. This eliminates the need for high-speed multipliers. The transform memories are additionally addressable by flags and tags associated with the location, attribute or object of interest. Different transformations take place depending on the values of the flags and tags. This allows flexible manipulation of the data. Z-buffering is done at high speed in parallel with the results being combined in efficient combiner circuits. In addition, this parallel operation permits the transformations themselves to be done in parallel.
    Type: Grant
    Filed: November 22, 1988
    Date of Patent: November 26, 1991
    Assignee: Reality Imaging Corporation
    Inventor: Robert H. Wake
  • Patent number: 5068803
    Abstract: A method and apparatus is described which fills in the pixels missed when drop-out occurs during the fill process of character contours. The character contour is decomposed into a series of rook moves. The pixel selected is the one more covered by the actual shape of the portion of the curve where the rook moves are coincident and dropout occurs. This is dependent upon the slope of each of the curves at the location of dropout. Preferably the length of the sequence of colinear consecutive rook moves is used to approximate the slopes of the curves. The target pixel of the longest sequence of colinear rook moves is more covered than its opposite pixel and therefore the target pixel is set. The target pixel for a rook move is the pixel in the winding direction (i.e., left or right direction) along the rook move. Thus the target pixel of the stronger rook moves will be set and added to the bit map image generated using a outline fill process.
    Type: Grant
    Filed: September 15, 1989
    Date of Patent: November 26, 1991
    Assignee: Sun Microsystems, Inc.
    Inventors: Jacobo Valdes, Eduardo Martinez
  • Patent number: 5068809
    Abstract: Desktop publishing system for preparing and managing documents in accordance with a model defined by graphic properties by using input document information and commands. This model is specified by a number of differently oriented sets of grid lines equidistantly oriented per set, for the positioning of said document information. On the basis of the last grid line used as reference line for graphic elements, the format data of the graphic elements positioned as well as to be positioned, and a certain spacing a grid line to be defined as the next reference line for the graphic elements to be positioned is selected from the grid lines following the first mentioned reference line.
    Type: Grant
    Filed: March 1, 1990
    Date of Patent: November 26, 1991
    Assignee: Oce-Nederland B.V.
    Inventors: Paulus W. E. Verhelst, Werner J. Winiger, Rene F. A. Collard
  • Patent number: 5065342
    Abstract: Apparatus for preparing image reproduction data from original image data which define visible representations to be reproduced, including a memory for storing original image data defining a plurality of visible representations each of which has at least one enclosed solid-imaging area to be solid-imaged, a first data preparing device for preparing solid-imaging data representative of the at least one solid-imaging area of a first kind of the visible representations, by effecting determination on the number of a winding count for the first kind of visible representations, based on the original image data, a second data preparing device for preparing solid-image data representative of the at least one solid-imaging area of a second kind of the visible representations, without effecting determination on the number of the winding count for the second kind of visible representations, based on the original image data, and a selector for selectively rendering operative one of the first and second data preparing mean
    Type: Grant
    Filed: March 1, 1990
    Date of Patent: November 12, 1991
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Yousuke Ito, Ichiro Sasaki
  • Patent number: 5065347
    Abstract: Method and apparatus of accessing and displaying hierarachical files on an electronic workstation screen that includes: (1) an Open Next-To operation that opens a separate window for a file to prevent the window from which the file was originally opened from being obscured, (2) a combination of both Open Next-To and Open-Within operations for opening different combinations, (3) "Chording" for displaying general options and depth display options to give the user a choice of a window OPEN method and hierarchical display depth as well as a choice of selecting "display all levels" format, (4) a FIND capability that enables finding of strings in a folder display, including forward and backward search and automatic text type conversion based on selection, (5) Iconic Pretty-Printing, that is, the icon optionally combined with text is offset as a function of its depth in a hierarchy including, (6) Folding of the display when the indentation reaches a desired column width, (7) a visual method of indicating the extent
    Type: Grant
    Filed: August 11, 1988
    Date of Patent: November 12, 1991
    Assignee: Xerox Corporation
    Inventors: Henry G. Pajak, Daniel S. Marder, Kenneth C. Byrne, Lee F. Breisacher
  • Patent number: 5060170
    Abstract: In display screen or system technology, a window is a viewing area on the video display. It may be the full screen region or a smaller region represented within a border of typically rectangular shape into which data from application programs and the like may be written for display. One or more windows may appear on the face of a video display screen. In the context of the present invention, the window areas are of variable size selected by the operator and resizing of the regions or areas within each variable window must be modified to suit the newly selected window size. Attributes associated with the regions to be placed within a given window include those for relative priority of display within the window, location within the window and the minimum dimensions of each region to be included within the window.
    Type: Grant
    Filed: August 9, 1989
    Date of Patent: October 22, 1991
    Assignee: International Business Machines Corp.
    Inventors: Nancy E. Bourgeois, Sandra L. Hause, Arwin B. Lindquist
  • Patent number: 5053944
    Abstract: A breakpoint apparatus incorporated in a single chip microprocessor. The apparatus permits breakpoints on specific references to either program instructions or data. The width of the breakpoint address can be varied, the apparatus includes a logic circuit for determining if the reference represented by the breakpoint address overlaps the current virtual address.
    Type: Grant
    Filed: October 3, 1990
    Date of Patent: October 1, 1991
    Assignee: Intel Corporation
    Inventor: Joseph C. Krauskopf
  • Patent number: 5051930
    Abstract: A documentation system for editing a document in which a plurality of document data of different forms coexist in a mixed fashion and which includes one or more pages each partitioned into a plurality of regions in accordance with difference edition processing procedures. The system includes a storage for storing the document data of the above-mentioned document structure, a display for displaying the document data as images, and a program executing unit for executing the programs to process the document data within the region being subjected to the edition. The edition processing programs are provided in correspondence with different edition processing procedures such that a given one of the edition processing programs processes the edition of the document data within one of the regions in the document image being displayed on the display unit.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: September 24, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Kuwabara, Hiroyuki Koreeda, Naomichi Nonaka, Keiichi Nakane
  • Patent number: 5051928
    Abstract: A color correction method for a video graphics system defines a region of color space within which target objects to be corrected lie. The region is defined automatically by positioning a target box within a representative portion of a target object within a video picture and computing from the pixels within the target box a range of color parameters which include the target object. A desired color for the target object is selected, and all pixels which are both within the video picture or a selected portion thereof and also within the defined region of color space are changed accordingly. Anti-aliasing is provided by scanning an area surrounding each pixel to determine the number pixels within the area which are within the defined region, and changing the color of each pixel according to the ratio of the number of pixels which lie within the defined region and the total number of pixels within the area.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: September 24, 1991
    Assignee: Dubner Computer Systems, Inc.
    Inventor: Michael S. Gruters
  • Patent number: 5050116
    Abstract: A keyboard for data processing equipment, the keyboard having a display screen and at least one key group switchable between different sets of functions. At least one image of the key group as well as function and meanings assigned to the keys of the key group appear on the display screen.
    Type: Grant
    Filed: September 3, 1987
    Date of Patent: September 17, 1991
    Inventor: Willi Stahnke
  • Patent number: 5047976
    Abstract: An operation circuit for M-bits parallel full addition includes partitioned adders and first and second multiplexers. Each of the first multiplexers selects one of paired provisional carry signals C.sub.ns-1 (1) and C.sub.ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C.sub.(s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C.sub.ns-1 to be progatatd from the s-th partitioned adder. Each of the second multiplexers generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k=n(s+1)-1, n(s+2) -1, . . . , n(s+l)-1) by referring to paired provisional carry signals Cr(1) (or Cr*(1); r=k-n=ns-1) and Cr(0) (or Cr*(0); k-n=ns-1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate l real carry signals Ck at the same time by selecting either the provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C.sub.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: September 10, 1991
    Assignee: Fujitsu Limited
    Inventors: Gensuke Goto, Hajime Kubosawa
  • Patent number: 5047958
    Abstract: A graphics subsystem (10) employs an image memory (12) that includes an on-screen part (44) and an off-screen part (46). The locations of the on-screen memory (44) are continually scanned to provide data to be displayed on a display device (16). The off-screen part (46) stores data that represent image segments that have been occluded by windowing. To transfer data between the on-screen part (44) and the off-screen part (46), an address generator (24) generates a sequence of two-dimensional addresses representing the two-dimensional positions of the pixels whose data are to be transferred. These addresses are converted to one-dimensional addresses by a simple circuit consisting of multiplexers (26 and 28), adders (30 and 32) and a multiplier (34).
    Type: Grant
    Filed: June 15, 1989
    Date of Patent: September 10, 1991
    Assignee: Digital Equipment Corporation
    Inventors: Todd R. Comins, Willem A. H. Engelse
  • Patent number: 5046179
    Abstract: A correlation computing device includes a higher-order bit elimination circuit which receives a digital input image signal and provides an output signal in which higher-order bits up to 50% have been eliminated as a maximum word length of a digital input image signal. A representative point preservation memory temporarily stores the output signal from the higher-order bit elimination circuit. A correlation determining circuit determines a correlation between a signal stored in the representative point preservation memory and the output signal from the higher-order bit elimination circuit. A minimum-value address decision circuit selects a minimum value of the correlation determined by the correlation determining circuit and determines a motion vector for the digital input image signal.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: September 3, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenya Uomori, Hirofumi Ishii, Atsushi Morimura
  • Patent number: 5046042
    Abstract: A data processing system processes digital information representing, for example, an image and supplied at a lower transfer rate from a data source such as an optical disc unit, to produce data in such a form as to be efficiently used by a device of a higher transfer rate such as a CRT display unit. The digital information includes a plurality of groups of data each representing, for example, a portion or a window of the image and added with control data for defining characteristics thereof. While the digital information is read out at a constant entire transfer rate, the plurality of groups of data are transferred at respective transfer rates which vary with a lapse of time. The control data of each group of data is separated therefrom, and the group of data and the separated control data are stored into first and second memories.
    Type: Grant
    Filed: March 24, 1986
    Date of Patent: September 3, 1991
    Assignee: Yamaha Corporation
    Inventors: Takashi Nitatori, Hirokazu Kato, Takatoshi Okumura, Shigemitsu Yamaoka
  • Patent number: RE33922
    Abstract: A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between external data and the data in the memory elements and the result of such operation is stored during a write cycle, thereby achieving a higher-speed operation.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: May 12, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyouda