Abstract: A control system and method for use with a sort accelerator having a rebound sorter as a merger in disclosed. The control system allows records to be efficiently and effectively transferred between processing elements and record storage elements of a rebound sorter. The control system allows consecutive groups of records to be sorted in the rebound sorter without mixing records from separate groups. The control system also pipelines records through the sorter by allowing different groups of records to input into the rebound sorter directly adjacent to each other.

Abstract: In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requ

Abstract: An assembler system translates a source program having a plurality of source code modules. The source code modules are evaluated in order to identify which source code module is the first source code module for which:(1) an object code module has not been assembled,(2) the source code module production time is later than the corresponding object code module production time, or(3) the source code module is positioned differently than it is in a recorded order.This first identified source code module, and the source code modules succeeding it, are assembled in accordance with the current assemble order.

Abstract: A system has a shared resource, such as a bus or memory, with which various devices may communicate upon a request being granted by an arbiter. In order to reduce the arbitration time, the arbiter is comprised of a state machine and latch which run asynchronously. Consequently, once one request has been granted and acted upon, the state machine will commence arbitration for any remaining requests.

Abstract: A perspective view of a pointer icon is displayed such that toward the middle of the display frame the icon appears to point toward the display surface, rather than toward an edge of the display frame. This creates an illusion that the icon, such as an arrowhead, is reversing its direction smoothly in three dimensional space. Although the display screen is only a two dimensional surface, the multiple icons can readily be configured to be shown in perspective and, therefore, appear to be three dimensional, without the requirement for gray scale or half tone display technology. The invention is readily implemented with conventional monochromatic or color graphics hardware commonly available for personal computers.

Abstract: An n-bit address selecting instruction read from a program ROM encludes a control bit part and an nm-bit (m<n) operand part. Data used for address selection is stored in k (k.ltoreq.m) extra bit positions of the control bit part. The data stored in the control bit part is supplied to a control bit data detecting circuit. The detecting circuit is responsive to the control bit data in the control bit part to produce first and second control signals. Detecting an address selecting instruction, the detecting circuit produces the first control signal so that a first data entry gate is enabled. When the first data entry gate is enabled, address selecting data stored in the operand part included in the address selecting instruction is written into an m-bit address counter. When the detecting circuit detects the address selecting instruction and that the number of bits of an address to be selected is "m+1" bits or more, the second control signal enables a second data entry gate.

Abstract: A distributed file management system (DFS) with a plurality of nodes and a plurality of files is disclosed. The DFS uses the UNIX operating system tree structure employing inodes (data structures containing the administrative information of each file) to manage the local files and surrogate inodes (s.sub.-- inode) to manage access to files existing on another node. In addition, the DFS uses a file access structure lock (fas.sub.-- lock) to manage multiple requests to a single file. The primary reason for the addition of the fas.sub.-- lock for each file is to avoid the problem of deadlocks. The inodes and s.sub.-- inodes use the fas.sub.-- lock to synchronize their accesses to a file and avoid a deadlock situation where both s.sub.-- inode and inode await the use of a file that is locked by the other.

Abstract: A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.

Abstract: A data structure for tabular data arranged in rows and columns. The data structure includes a header portion including a generic columnar processing information table, and a data portion for storing data in rows, the data portion further identifying a table containing generic columnar processing information to be used in processing selected cells in the row. In a refinement, each row in the data structure includes a row header including a row number and at least one cell, the row number identifying a row in a table for the cell. As a further refinement, each cell includes a header portion and a value portion, the header portion containing a cell number identifying a column in a table for the cell.

Abstract: A multi-processing system of the type having a plurality of MSUs is provided with a support controller in each MSU. Each of the MSUs is provided with a plurality of the interface registers, one for each associated MSU to be connected to the master MSU. Each support controller in each MSU is provided with an initial program load (IPL) controller and each IPL controller is provided with a scan settable control coupled to an external keyboard or console which permits unique scan settable information to be loaded into the IPL controller for setting the interface registers and for interconnecting the MSUs in a desired multi-processing configuration.

Abstract: A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems in which each processing module has a local cache. Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibited by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

Abstract: A clock pulse generator for a one-chip microprocessor permits the microprocessor to be operated on two different power sources by effectively using a single source of clock pulses, a clock pulse divider and gate circuits to gate a specific sequence of pulses to the microprocessor. The period of a slowest clock pulse signal after division is integrally related to the periods of the faster clock pulse signals so that the pulse signals are synchronously provided.

Abstract: In a text editing device having a function capable of automatically executing a line feed operation, such line feed operation is inhibited during input operations which are sequentially executed at a high speed, with the inhibit operation being released when a predetermined condition, for example, input operation at a right hand margin or of a space or hyphen at a hotzone or the like, is satisfied. Thus, the time for character display corresponding to the inputted data is shortened.

Abstract: A method and device for coded entry of Chinese character text data into a word processing, display, printing, telecommunication, etc. system.

Abstract: An improved method manages the storage of document images so as to minimize the average access time while minimizing overall storage costs, consistent with the probable usage of the documents for a particular application. Document images can be selectively stored on high speed, low capacity magnetic DASD or alternately on low speed, high capacity optical storage. DASD storage is more expensive than optical storage for a document image. By characterizing the probable use of a document image in association with a case processing work flow within which the document image is to participate, optimum document storage can be achieved. When a case has a predefined plurality of document image types, and a particular document image type is missing, the case can be placed in a pending state while awaiting the receipt of the missing document image. In the pending state, the documents which are members of the pended case can be removed from the DASD and retained on the optical storage device.

Abstract: A list type data storing and retrieving system includes an analyzing circuit for analyzing a structure of list type data and outputting symbols constituting the data and appearance position data of each symbol in each list type data, a storage circuit for storing the position data output from the analyzing circuit, symbols respectively assigned to the position data, and at least one identifier set for the symbols assigned to the position data to specify the input list type data, and a retrieval circuit for reading out sets of identifiers including the same symbols and position data as symbols constituting list type data to be input and retrieved and corresponding position data or identifiers including variable symbols in position data having a higher order than that of the position data from the storage means with respect to all symbols constituting the input list type data, and outputting list type data specified by identifiers common to all the symbols as unifiable candidates.

Abstract: A process controls the routing of an arriving job in a job stream through a switch to one of a plurality of processing stations. At predetermined time intervals, occupancy factors associated with the stations are computed as determined by station configuration information and job stream information. Upon the arrival of an incoming job, the occupancy factors corresponding to the current processing status of the stations are used to compute station utilization values. The station having the minimum utilization value is selected to receive and process the incoming job provided this minimum value is less than a preselected threshold; otherwise, the incoming job is denied processing permission.

Abstract: A system for transferring data between a pair of data processing units having system buses includes a plurality of memories in each of the data processing units; each memory having a random access portion and an associated sequential access portion; means for transferring data between each of the random access portions of each of the memories and its associated sequential access portion; and means connecting the sequential access portions of each of the memories in one of the data processing units to the sequential access portions of the other of said data processing units to permit data flow therebetween; the data flow between the sequential access portions of said memories occurring asynchronously of the remainder of the system so that the data processing units can utilize their system buses during such data flow.

Abstract: A secure read only memory in which an external address of (n-m) bits is applied to an address controller which converts the external address into an n bit internal address which is applied to a read only memory to obtain data stored in the read only memory at the address locations. The address controller includes detector circuits for detecting improper accesses to the memory. In response to an improper access to the memory, the memory controller will produce an improper access signal which improper access signal is used to terminate operation of the system or to modify the address so that the data produced in response to the external address has essentially no direct reproducable relationship to the actual address of the memory location of the random access memory where the data is stored.

Abstract: A functional unit composed of parallel data processing paths implemented in relatively low speed digital logic. A data processing path is designed in a digital logic family of high integration but relatively low speed. The path is designed to be clocked by a data processing clock where the frequency of the data processing clock is substantially the system clock divided by the number of parallel implementations of the data processing path.