Abstract: The method of the present invention is a method of forming a silicon-based semiconductor layer by introducing a source gas into a vacuum vessel and forming a silicon-based semiconductor layer containing a microcrystal on a substrate introduced into the vacuum vessel by plasma CVD, which comprises a first step of forming a first region with a source gas containing halogen atoms, and a second step of forming a second region on the first region under a condition where the source gas containing halogen atoms in the second step is lower in gas concentration than that of the first step, thereby providing a method of forming a silicon-based semiconductor layer having an excellent photoelectric characteristic at a film forming rate of an industrially practical level and a photovoltaic element using the silicon-based semiconductor layer formed by the method.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of both hydrogen and fluorine as process gases in the reactive mixture of a plasma-containing CVD reactor. The process gas also includes dielectric forming precursors such as silicon and oxygen-containing molecules.

Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.

Abstract: A TFT-LCD device has a plurality of scanning lines formed by a first level metallic layer, a plurality of data lines formed by a second level metallic layer, and an array of pixels each having a TFT and a pixel electrode made of a third level ITO layer. Each pixel further includes a shied ring formed by the second level metallic layer for suppressing variance in the parasitic capacitances formed between the pixel electrode and other conductive layers. The suppression of the variance in the parasitic capacitances reduces the feed-through voltage, thereby improving the display performance of the TFT-LCD device.

Abstract: A light shield apparatus and formation method for preventing the transmission of incident light towards active devices of the display. In one embodiment, the present invention recites forming a plurality of metal pixels wherein adjacent ones of the plurality of metal pixels have a gap region disposed therebetween. The present embodiment then recites depositing a light absorbing antireflective coating material within the gap region to form a light shield such that transmission of incident light through the gap region towards underlying active devices is reduced. Hence, the present embodiments also reduce problems associated with Liquid Crystal alignment difficulty and passivation integrity (cracking of thin passivation). Next, the present embodiment deposits a thin composite passivation layer above the plurality of metal pixels and the antireflective coating material.

Abstract: The present invention comprises the steps of forming a connection hole in an interlayer insulating film including an organic insulating film; forming an inorganic film covering on an upper surface of the interlayer insulating film and an inner surface of the connection hole; forming an organic film for filling inside the connection hole on an inorganic film; removing the organic film inside the connection hole so as to leave a part of the organic film at a bottom of the connection hole; forming a wiring trench connecting to the connection hole in the interlayer insulating film; removing the organic film inside the connection hole; removing the inorganic film; and forming a trench wiring by filling a conductive material in the wiring trench and inside the connection hole and forming a plug continuing from the trench wiring.

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

Abstract: A temperature measuring method for a target substrate to be thermally processed in a semiconductor processing apparatus under a predetermined process condition is provided. This method includes the steps of detecting a heat flux supplied from at least part of the target substrate and detecting a temperature of a sensor by using the sensor facing the target substrate, and calculating a temperature of the target substrate from a parameter, including a thermal resistance between the sensor and the target substrate under the predetermined process condition, the detected heat flux, and the temperature of the sensor. The sensor is arranged opposite to heating means, through the target substrate, which heats the target substrate. The parameter may be obtained in advance by calibration.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a light sensitivity of the photodiode. That is, the epitaxial layer, in which the photodiode is formed, has a trench or a protrusion. Also, in the pinned photodiode, since the P0 diffusion layer is directly in contact with the P-epi layer, the two P-type layers have the same potential and then it may operate in a low voltage.

Abstract: A semiconductor device comprising a metal-oxide-semiconductor field-effect transistor well controllably brings the work function of a gate electrode close to the intrinsic mid gap energy of silicon, thereby lowering the concentration of impurities in a channel. By this, the deterioration of carrier mobility is prevented and a metal-oxide-semiconductor field-effect transistor is obtained. A gate electrode has a multi-layer structure of a p-type polycrystalline or a single-crystalline germanium film 3 and a low resistance conductive film 4.

Abstract: A method of forming a doped polycrystalline silicon gate in a Metal Oxide Semiconductor (MOS) device. The method includes forming first an insulation layer on a top surface of a crystalline silicon substrate. Next, an amorphous silicon layer is formed on top of and in contact with the insulation layer and then a dopant is introduced in a top surface layer of the amorphous silicon layer. The top surface of the amorphous silicon layer is irradiated with a laser beam and the heat of the radiation causes the top surface layer to melt and initiates explosive recrystallization (XRC) of the amorphous silicon layer. The XRC process transforms the amorphous silicon layer into a polycrystalline silicon gate and distributes the dopant homogeneously throughout the polycrystalline gate.

Abstract: After a p seat electrode is laminated on a light-transmissive electrode, the two electrodes are heated at a relatively low temperature to thereby remove gas (degassing) from between the two electrodes. Then, the two electrodes are alloyed with each other at a high temperature.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad.

Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.

Abstract: A liquid crystal display (LCD) having an oblique electric field while a voltage is applied between the upper plate and the lower plate of the LCD is disclosed. The LCD includes a first regulating device of the upper plate and the second regulating device of the lower plate. As no voltage between the upper and lower plate, the liquid crystal molecules in the proximity of the first and the second regulating device are perpendicular to the upper and the lower plate. After a voltage is applied, an oblique electric field is produced by these regulating devices. The liquid crystal molecules are then rotated to parallel to the upper and lower plates because of the oblique electric field. The first and second regulating devices are bumps made of dielectric material or slits of electrodes.

Abstract: A defect-free film is formed on a surface of a protrusive electrode. An immersion Au film is formed on the surface of the protrusive electrode, after a gap which an immersion Au plating liquid can enter evenly is formed between a protrusive electrode made of Ni or a Ni alloy on an electrode pad made of Al or mainly made of Al and a protective coat by etching.

Abstract: A thin-film capacitor device for performing temperature compensation is manufactured by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric thin-film has a thickness tN, wherein tN={&egr;0&tgr;t0t/(C/S)}·{1/(&tgr;/&kgr;)}, wherein C/S represents a sheet capacitance, &egr;0 represents the dielectric constant of vacuum, &tgr;t0t represents a desired temperature coefficient of capacitance, &tgr; represents the temperature coefficient of capacitance of the second dielectric thin-film, and &kgr; represents the relative dielectric constant of the second dielectric thin-film, a target value of a grain size of the second dielectric thin-film is determined by selecting the grain size satisfying the formula (&tgr;/&kgr;)/(&tgr;g/&kgr;g)>1, wherein &tgr;g represents the temperature coefficient of capacitance of the principal crystal grain, and &kgr;g represents relative dielectric constant of the principal crystal grain, and the seco