Abstract: The present invention relates to a semiconductor light-emitting device used for optical transmission (particularly for IEEE 1394) and displays and the like. More specifically, an object of the present invention is to provide a semiconductor light-emitting device capable of emitting the light with a high efficiency by extending a distance from an active layer to a boundary having poor crystal quality due to Group V elements As and P exchange to suppress deterioration in crystal quality of the active layer.

Abstract: A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop.

Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.

Abstract: A method for an efficient extended pulse laser annealing process is provided. The method comprises: supplying a substrate with a thickness; selecting an energy density; selecting an extended pulse duration; laser annealing a substrate region; in response to cooling the substrate region, crystallizing the substrate region; and, efficiently extending the lateral growth of crystals in the substrate region. When the substrate has a thickness of approximately 300 Å, the energy density is selected to be in the range of 400 to 500 millijoules pre square centimeter (mJ/cm2). The pulse duration is selected to be in the range between 70 and 120 nanoseconds (ns). More preferably, the pulse duration is selected to be in the range between 90 and 120 ns. Most preferable, the pulse duration is approximately 100 ns. Then, efficiently extending the lateral growth of crystals in the substrate region includes laterally growing crystals at a rate of approximately 0.029 microns per nanosecond.

Abstract: In a method for manufacturing a thin-film capacitor for performing temperature compensation by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric thin-film has a thickness tN, wherein tN={∈0&tgr;t0t/(C/S)}·{1/(&tgr;/&kgr;)}, wherein C/S represents a sheet capacitance, ∈0 represents the dielectric constant of vacuum, &tgr;t0t represents a desired temperature coefficient of capacitance, &tgr; represents the temperature coefficient of capacitance of the second dielectric thin-film, and &kgr; represents the relative dielectric constant of the second dielectric thin-film, a target value of a grain size of the second dielectric thin-film is determined by selecting the grain size satisfying the formula (&tgr;/&kgr;)/(&tgr;g/&kgr;g)>1, wherein &tgr;g represents the temperature coefficient of capacitance of the principal crystal grain, and &kgr;g represents relative dielectric constant of the principal crystal grain, and

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.

Abstract: Within a method for fabricating a microelectronic fabrication comprising a topographic microelectronic structure formed over a substrate, there is implanted, while employing a first ion implant method and while masking a portion of the substrate adjacent the topographic microelectronic structure but not masking the topographic microelectronic structure, the topographic microelectronic structure to form an ion implanted topographic microelectronic structure without implanting the substrate. There is also implanted, while employing a second ion implant method, the portion of the substrate adjacent the topographic microelectronic substrate to form therein an ion implant structure. The method is particularly useful for fabricating source/drain regions with shallow junctions within field effect transistor (FET) devices.

Abstract: MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP.

Abstract: Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.

Abstract: A temperature measuring method for a target substrate to be thermally processed in a semiconductor processing apparatus under a predetermined process condition is provided. This method includes the steps of detecting a heat flux supplied from at least part of the target substrate and detecting a temperature of a sensor by using the sensor facing the target substrate, and calculating a temperature of the target substrate from a parameter, including a thermal resistance between the sensor and the target substrate under the predetermined process condition, the detected heat flux, and the temperature of the sensor. The sensor is arranged opposite to heating means, through the target substrate, which heats the target substrate. The parameter may be obtained in advance by calibration.

Abstract: High contrast alignment marks that can be flexibly located on a semiconductor wafer are disclosed. The wafer has a first layer and a second layer. The first layer has a light-dark intensity and a reflectivity. The second layer is over the first layer, and has a light-dark intensity substantially lighter than that of the first layer, and a higher reflectivity than that of the first layer. The first layer may be patterned to further darken it. The second layer contrasts visibly to the first layer, and is patterned to form at least one or more alignment marks within the second layer. The first layer may be a metallization layer, such as titanium nitride, whereas the second layer may be a metallization layer, such as aluminum or copper.

Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planerization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 706 that serves as a foundation for bottom contact layers 708 and a polyimide 700 coating. An ohmic metal contact 702 and emitter metal contact 704 protrude above the polyimide 700 coating exposing the ohmic metal contact 702 and emitter metal contact 704. The contacts are capped with an etch resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.

Abstract: A silicon nitride layer is formed over transistor gates while the processing temperature is relatively high, typically at least 500° C., and the pressure is relatively high, typically at least 50 Torr, to obtain a relatively high rate of formation of the silicon nitride layer. Processing conditions are controlled so as to more uniformly form the silicon nitride layer. Generally, the ratio of the NH3 gas to the silicon-containing gas by volume is selected sufficiently high so that, should the surface have a low region between transistor gates which is less than 0.15 microns wide and have a height-to-width ratio of at least 1.0, as well as an entirely flat area of at least 5 microns by 5 microns, the layer forms at a rate of not more than 25% faster on the flat area than on a base of the low region.

Abstract: A Group-III nitride semiconductor light-emitting diode having an electrically conducting silicon (Si) single crystal substrate having on an upper surface thereof at least a light-emitting part having a pn-heterojunction structure composed of a Group-III nitride semiconductor, which light-emitting part is stacked via an intermediate layer composed of a metal or a semiconductor, the single crystal substrate having a back surface electrode on a back surface thereof, a surface electrode on an upper surface of the light-emitting part and a perforated part formed by eliminating the Si single crystal substrate in a region exclusive of the back surface electrode on the back surface of the single crystal substrate and a method of manufacturing thereof are disclosed.

Abstract: In a method of fabricating a semiconductor device having a gate all around(GAA) structure transistor, an SOI substrate having a SOI layer, a buried oxide layer, and a bottom substrate is prepared. The SOI layer is patterned to form an active layer pattern. An etch stopping layer having an etch selectivity with respect to the buried oxide layer and the active layer pattern is stacked on the active layer pattern. The etch stopping layer pattern is patterned and removed at the gate region crossing the active layer pattern at the channel region, to form an etch stopping layer pattern and to expose the buried oxide layer. The buried oxide layer is isotropically etched using the etch stopping layer pattern as an etch mask to form a cavity at the channel region bottom of the active layer pattern. A conductive material fills the cavity and a space between the etch stopping layer pattern at the gate region. In this manner, the number of photolithography processes required for forming the device is reduced.

Abstract: An edge illuminated epilayer waveguide phototransistor including a subcollector layer formed from an epitaxially grown quaternary semiconductor material, such as heavily doped InGaAsP. A collector region of undoped InGaAs is epitaxially grown on the subcollector layer. A base region of moderately doped InGaAs is epitaxially grown on the collector layer. An emitter region, including a doped InGaAsP layer, a doped InP layer, and a heavily doped InGaAs emitter contact layer, is epitaxially grown on the base layer. The various layers and regions are formed so as to define an edge-illuminated facet for receiving incident light. Also, the base does not have an ohmic contact so that the base thickness can be minimized. Finally, the base doping concentration is minimized so that the gain-bandwidth product can be maximized.

Abstract: A buffer layer with a composition of AlaGabIncN (a+b+c=1, a, b, c≧0) and a multilayered thin films with a composition of AlxGayInzN (x+y+z=1, x, y, z≧0) are formed in turn on a substrate. The Al component of the Al component-minimum portion of the buffer layer is set to be larger than that of at least the thickest layer of the multilayered thin films. The Al component of the buffer layer is decreased continuously or stepwise from the side of the substrate to the side of the multilayered thin films therein.

Abstract: Single-electron transistors include first and second electrodes and an insulating layer between them on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography. An electrically-gated single-electron transistor may be formed, wherein a gate electrode is provided on the at least nanoparticle opposite the insulating layer end. Alternatively, a chemically-gated single-electron transistor may be formed by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Arrays of single-electron transistors also may be formed on the substrate.

Abstract: A method for forming a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. A semiconductor device is provided with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film. The SOI substrate includes a buried oxide film and a SOI layer provided in succession on a silicon substrate.