Abstract: A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.

Abstract: A display device includes: a substrate including a display region and a peripheral region, wherein the peripheral region is adjacent to the display region; a first transistor disposed on the peripheral region, wherein the first transistor includes a first semiconductor layer and the first semiconductor layer is a silicon semiconductor layer; and a second transistor disposed on the display region, wherein the second transistor includes a second semiconductor layer and the second semiconductor layer is an oxide semiconductor layer, wherein the first transistor is electrically connected to the second transistor.

Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack over the substrate, a first epitaxial layer, a second epitaxial layer, first array common sources (ACS's), and second ACS's. The layer stack includes first stack layers and second stack layers that are alternately stacked. The first epitaxial layer is deposited on a side portion of a channel layer that extends through the layer stack. The second epitaxial layer is deposited on the substrate. The first ACS's and a portion of the layer stack are between the second ACS's.

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.

Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.

Abstract: The current disclosure describes semiconductor devices, e.g., transistors including a thin semimetal layer as a channel region over a substrate, which includes bandgap opening and exhibits semiconductor properties. Described semiconductor devices include source/drain regions that include a thicker semimetal layer over the thin semimetal layer serving as the channel region, this thicker semimetal layer exhibiting metal properties. The semimetal used for the source/drain regions include a same or similar semimetal material as the semimetal of the channel region.

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

Abstract: A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

Abstract: An integrated circuit structure including a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure; an EMF shield enclosing the substrate, the gallium nitride layer and the photoconductive semiconductor switch laterally disposed alongside the transistor on the gallium nitride layer integrated into the integrated circuit structure; and a signal line electronically coupled with the photoconductive semiconductor switch, the signal line penetrating the EMF shield.

Abstract: A display device is provided. The display device includes: a substrate including a display area including pixels at which an image is displayed and a peripheral area at which the image is not displayed, the peripheral area disposed outside the display area. In the peripheral area, the display device further includes: a plurality of thin film transistors connected to the pixels and with which operation of the pixels is tested, the thin film transistors including gate electrodes arranged separated from each other on the substrate; and a bridge wiring electrically connecting adjacent gate electrodes of the plurality of thin film transistors to each other.

Abstract: In an image display element, a side surface of a nitride semiconductor is covered with a reflection material inclined so as to open in a light emitting direction, wavelength conversion units are surrounded by partition walls, and side surfaces of the partition walls facing the wavelength conversion units are reflection surfaces inclined so as to open in the light emitting direction.

Abstract: A packaged antenna circuit structure suitable for 5G use includes a shielding layer, an electronic component, conductive pillars, a first insulation layer, a first stacked structure, an antenna structure, and a second stacked structure. The shielding layer defines a groove to receive the electronic component. The conductive pillars on the shielding layer surround the groove. The first insulation layer covers the shielding layer, the electronic component, and the conductive pillars. The first stacked structure is stacked on a side of the first insulation layer and includes a ground line connecting to the conductive pillars. The antenna structure is stacked on a side of the first stacked structure away from the first insulation layer and connected to the electronic component by the first stacked structure. The second stacked structure is stacked on a side of the first insulation layer away from the first stacked structure.

Abstract: An image pickup element using an APD is provided. The image pickup element has a first substrate, a second substrate, and a connector. The first substrate is provided with a plurality of light receivers having the APD. The second substrate has a pixel circuit that corresponds to each of the APDs. Additionally, the connector electrically connects the APD and the pixel circuit corresponding to the APD.

Abstract: Light-emitting devices with active electrical elements and light-emitting diodes (LEDs) are disclosed. LEDs may be mounted on an active electrical element such that the LEDs are within peripheral edges of the active electrical element. Contact pads may be arranged on the active electrical element for receiving external power and communication signals for active control of the LEDs. A light-transmissive carrier may be positioned over the active electrical element and the LEDs. Electrical traces of the carrier may be configured to electrically connect with the contact pads to route external power connections and communication signals for the active electrical element. Other electrical traces of the carrier may form a touch sensing element that is electrically coupled with the active electrical element. Active electrical elements with LEDs provided thereon may form compact sizes for use as active LED pixels configured for active-matrix addressing within an LED display.

Abstract: A semiconductor storage device includes a memory cell array including a stacked body having insulating layers and conductive layers that are alternately stacked. The memory cell array includes a cell area and a contact area provided adjacent the cell area. The semiconductor storage device includes: a circuit below the memory cell array; a source layer between the memory cell array and the circuit; a first contact in the contact area, and coupled to the circuit; a second contact over the cell area and the contact area; a first wiring extending in a direction intersecting an extending direction of the second contact in the contact area; a second wiring above the second contact, extending along the second contact in the contact area, and connected to the first wiring; and third contacts between the second wiring and the second contact.

Abstract: The present disclosure provides a display substrate which includes: a plurality of pixel units, at least one of which includes a light emitting diode and a drive circuit. The light emitting diode includes a cathode; the display substrate further includes an auxiliary electrode layer including at least one auxiliary electrode. The auxiliary electrode is disposed in at least one of the pixel units. The auxiliary electrode is electrically connected with the cathode of the light emitting diode which is located in the same pixel unit as the pixel unit that the auxiliary electrode is located in, and the auxiliary electrode covers at least a portion of the drive circuit in the pixel unit that the auxiliary electrode is located in. The auxiliary electrode is made of an opaque conductive material, so as to block light irradiated at the portion of the drive circuit that is covered by the auxiliary electrode.