Patents Examined by Donald M Lair
  • Patent number: 7042227
    Abstract: A method and system for determining a torque current in an electric machine coupled to a polyphase bus. The method comprises: detecting a rotational position of the electric machine with a position encoder; controlling an inverter comprising a plurality of switching devices, the inverter having an input coupled to a direct current bus, and an output coupled to the polyphase bus. Where the inverter is responsive to commands from a controller coupled to the inverter and to the position encoder. The method also includes measuring a current from the direct current bus; and capturing the current at a predefined interval of time.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: May 9, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Sayeed A. Mir, Dennis B. Skellenger, Roy Alan McCann, Mark Philip Colosky
  • Patent number: 6975123
    Abstract: A method and apparatus are disclosed which are operable to determine a capacitance associated with at least one piezoelectric element in an dual actuator disk drive. The capacitance information is used to adjust a driver used to drive the piezoelectric element. Capacitance is determined by supplying a predetermined current into the piezoelectric element(s) for a predetermined time period. A voltage associated with the piezoelectric element(s) is measured following the predetermined time period. The capacitance of the piezoelectric element(s) is then calculated based on the measured voltage, the current supplied, and the predetermined time period.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: December 13, 2005
    Assignee: Maxtor Corporation
    Inventors: Keith Malang, Larry Hutsell
  • Patent number: 6859042
    Abstract: A method and apparatus for detecting electrical arcs in an electrical system having a periodic power supply is disclosed. A method according to the invention compares instantaneous values of a monitored waveform both with (a) their past values at corresponding phases of the AC supply waveform, and (b) their future values at corresponding phases of the AC supply waveform. The monitored waveform is delayed or stored to allow such comparisons in near real time, to produce an output which is only slightly delayed behind the monitored waveform. An apparatus according to the present invention discloses a sampling circuit that samples electrical signals indicative of transient load conditions to produce a sampling circuit output. A storage device receives the sampling circuit's output and stores a time history of that output over an interval.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: February 22, 2005
    Assignee: Hendry Mechanical Works
    Inventor: Michael T. Parker
  • Patent number: 6851849
    Abstract: At least one forward-biased semiconductor diode having a potential barrier is used as a temperature sensor whose sensitivity can be finely adjusted. An operational amplifier circuit (A1) is used to apply a bias voltage of DC or rectangular waveform to a semiconductor diode (D) having a potential barrier used as a temperature sensor. In view of the fact that the temperature sensitivity of the semiconductor diode (D) depends on the height of its potential barrier, the forward bias voltage applied from a bias circuit (2) directly to the semiconductor diode (D) is finely adjusted to obtain desired temperature sensitivity. The output voltage of the sensor is associated with a current, having an exponential temperature dependence, which flows in the semiconductor diode (D) with the forward bias being fixed.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: February 8, 2005
    Assignee: Japan Science and Technology Agency
    Inventor: Mitsuteru Kimura
  • Patent number: 6853202
    Abstract: Embodiments of the present invention relate to a method and mechanism for testing wire bonds in an integrated circuit package. The method comprises bonding an integrated circuit silicon die to a package substrate. Next, wire connections are formed between pads in the integrated circuit silicon die and contact leads in the package substrate and testing each of the wire connections in order to detect non-stick failures using electrical continuity provided by the integrated circuit silicon die substrate. Electrical continuity is provided through dedicated pads in the package substrate that contact the underside of the silicon die substrate. The dedicated contact pads in each package substrate of the molded laminate array are connected to each other and to the mold gate. The continuity thus provided allows a non-stick-on-pad test by ensuring continuity between the wire spool through the die to the mold gate.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: February 8, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bo Chang, Vani Verma
  • Patent number: 6850051
    Abstract: In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: February 1, 2005
    Assignee: McGill University
    Inventors: Gordon W. Roberts, Antonio H. Chan
  • Patent number: 6842029
    Abstract: A multi-probe assembly includes a chuck assembly configured to receive a back or front surface of a semiconductor wafer. A multi-probe holder has a plurality of probes each having an elastically deformable conductive tip movable into contact with a front surface of a dielectric or a front surface of a semiconducting material. A means applies an electrical stimulus to each tip, measures a response to the electrical stimulus, and determines at least one electrical property of the dielectric and/or the semiconducting material. A method for measuring at least one electrical property applies a probe (or plurality of probes) having an elastically deformable conductive tip to a scribe line(s). An electrical stimulus is applied to the probe or one of the probes with the remaining probes grounded. A response to the electrical stimulus is measured and at least one electrical property of the semiconductor wafer is determined from the response.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: January 11, 2005
    Assignee: Solid State Measurements, Inc.
    Inventor: William H. Howland
  • Patent number: 6838888
    Abstract: A system for monitoring water concentration in gaseous sample is disclosed. It is readily applicable in the synthesis of biopolymer arrays/microarrays involving the use of water-sensitive reagents. A flow cell is provided in which a capacitance sensor is placed separate from a production or synthesis environment. Sample and dry gas may be provided to the flow cell via conduits and valves or a manifold system. Dry gas, such as N2, is used to dry the sensor or simply to maintain it in a dried condition. The same gas may be used to drive an optional venturi pump to draw sample for measurement into the cell from the synthesis environment.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 4, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: Bill J. Peck
  • Patent number: 6838884
    Abstract: A timing output panel may include a rear portion and a front portion. The rear portion may include a number of network connectors respectively configured to connect to a number of network elements, and at least one timing connector connected to the number of network connectors and configured to connect to synchronization electronics. The front portion may include a number of equipment jacks corresponding to and electrically connected to the number of network connectors. The equipment jacks may facilitate temporary connection of cables for testing or patching signals to the network elements. The front portion also may include a number of timing jacks corresponding to and electrically connected to the at least one timing connector. The timing jacks may facilitate temporary connection of cables for testing the synchronization electronics or patching to the equipment jacks.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: January 4, 2005
    Assignee: WorldCom, Inc.
    Inventor: Lawrence N. Dagate
  • Patent number: 6836126
    Abstract: An offset calibration system of a control loop at least comprises a pre-amplifier circuit and a post-amplifier circuit. The pre-amplifier circuit generates a pre-output signal and then transmits the pre-output signal to the post-amplifier circuit to amplify. The offset calibration system comprises a comparator, an offset calibration module, and a determination circuit. The comparator compares the pre-output signal with a predetermined pre-reference signal to generate a pre-compared signal. The offset calibration module stores a predetermined and adjustable offset calibration value for adding to the pre-output signal. The determination circuit adjusts the offset calibration value based on the pre-compared signal, so the offset calibration value can be added to the pre-output signal dynamically to compensate and calibrate the offset of the pre-output signal caused by the pre-amplifier circuit to avoid the post-amplifier circuit amplifying the offset of the pre-output signal again.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: December 28, 2004
    Assignee: MediaTek Inc.
    Inventor: Yung-Yu Lin
  • Patent number: 6833725
    Abstract: On a basic measurement unit arranged in a lattice shape on a chip, a resistance measurement circuit, a capacity measurement circuit, an n-type MOS transistor measurement circuit, a p-type MOS transistor measurement circuit, and a ring oscillator measurement circuit are mounted by several tens of patterns. Each measurement circuit mounted by several tens of patterns is connected to a measurement bus to constitute a measurement bus net in accordance with measured items. Switching of connection of the measurement bus net with a measurement terminal pad is electrically controlled properly by X, Y address selection signals outputted from X, Y address decoders to X, Y address selection signal lines.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: December 21, 2004
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Shin-ichi Ohkawa, Masakazu Aoki
  • Patent number: 6831468
    Abstract: Methods and apparatuses are described for detecting volumetric moisture content and conductivity in various media based on a time-domain reflectometry (TDR) system wherein successive fast transitions are injected into a transmission line immersed in a medium of interest, and a characteristic received waveform is digitized and analyzed by continuously sampling multiple received waveforms at short time intervals. One method transmits a timing signal along a shielded transmission line while a coincident signal is transmitted through the medium of interest. Another method propagates the waveform along a transmission line, that may be either shorted or open-ended, and observes a reflected, rather than transmitted, waveform with a receiver connected to the same end of the transmission line as the transmitter.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: December 14, 2004
    Assignee: Technical Development Consultants, Inc.
    Inventors: Scott K. Anderson, Hyrum S. Anderson
  • Patent number: 6828793
    Abstract: To eliminate in structure a parasitic capacity formed between a polycrystalline silicon film resistor and a semiconductor substrate, and to provide a battery voltage detecting circuit capable of surely detecting a battery voltage. A layer such as a well which is insulated from a semiconductor substrate is disposed on the semiconductor substrate just below a polycrystalline silicon film resistor, and a potential of the layer is set to be a stable potential which is not influenced by a potential of the polycrystalline silicon film resistor or a detecting operation of a battery. With this structure, no parasitic capacity is eliminated in structure, thereby being capable of surely detecting the battery voltage.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: December 7, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Takeshi Mashiko
  • Patent number: 6825670
    Abstract: The present invention relates to a method for testing a conductor element (20) applicable to locating a continuity defect of the conductor element, the conductor element having, relative to a reference conductor, an insulation resistance and a leak capacitance. According to the present invention, the method comprises a step of injecting into the conductor element at least two currents (i1, i2) of different frequencies by means of a current or voltage generator (23), one terminal of which is connected to the reference conductor, at least one step of measuring the amplitudes of currents at one measuring point (Pi) chosen along the conductor element, and a step of calculating the imaginary part of currents and/or calculating the leak capacitance of the conductor element downstream from the measuring point (P1).
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: November 30, 2004
    Assignee: Socrat
    Inventor: Jean Bussinger
  • Patent number: 6825672
    Abstract: A cable testing system and method tests cable and determines status, cable length and reflection amplitude. The test module includes a pretest state machine that senses activity on the cable and enables testing if activity is not detected for a first period. A test state machine is enabled by the pretest state machine, transmits a test pulse on the cable, measures a reflection amplitude and calculates a cable length. The test module determines the status based on the measured amplitude and the calculated cable length. A lookup table includes a plurality of sets of reflection amplitudes as a function of cable length. The test module determines the status using the lookup table, the reflection amplitude and the cable length.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 30, 2004
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Yiqing Guo
  • Patent number: 6819121
    Abstract: An apparatus and a method for determining the cure state of thermosetting concrete using time domain reflectometry. A miniature capacitor is constructed at the end of a coaxial transmission line which is immersed in the curing concrete so that the concrete is the dielectric of the capacitor, and step function voltage pulses are fed to the transmission line, while the reflected signal from the line is monitored. The amplitude at several points of the reflected pulses, which are related to the free water and bound water in the concrete and indicate the degree of cure, are fed to a computer for interpretation and display.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: November 16, 2004
    Assignee: Material Sensing & Instrumentation, Inc.
    Inventors: Nathaniel E. Hager, III, Roman Domszy
  • Patent number: 6815955
    Abstract: A circuit breaker test device for testing a circuit breaker, and also for testing the branch circuit of which the circuit breaker is a part. The circuit breaker test device includes a switch that controllably short-circuits the branch circuit. A controller causes the switch to short circuit the branch circuit. A timer, responsive to operation of the controller, causes the switch to cease short-circuiting the branch circuit after a particular test time. An impedance value of the branch circuit is determined. The controller is enabled only if the impedance value is within predetermined limits. The timer is capable of establishing a variable test time.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: November 9, 2004
    Assignee: K.O. Devices, Inc.
    Inventor: Charles D. O'Neal, III
  • Patent number: 6815657
    Abstract: A reading apparatus has a sensor unit which is arranged on a substrate to read an object to be detected, a driver circuit unit which is arranged on the substrate to supply a drive signal for driving the sensor unit, and a static electricity protection portion, which is formed to cover at least a portion of the upper surface of the driver circuit unit, and at least a portion of which has electrical conductivity.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: November 9, 2004
    Assignee: Casio Computer Co., Ltd.
    Inventors: Tsuyoshi Toyoshima, Shigeru Morikawa, Yasushi Mizutani
  • Patent number: 6806697
    Abstract: A probe for connecting a device under test to a measurement device that corrects for dc errors and noise generated by the current flowing through the ground shield of a transmission line used by the probe. The probe identifies a voltage drop in the ground preferably using an additional line between the device under test and the measurement device. The signal provided to the measurement device is corrected based on the identified voltage drop.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: October 19, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Michael T. McTigue
  • Patent number: 6803774
    Abstract: A meter for measuring the root-mean-squared potential of an AC signal characterized by a frequency f is disclosed. The meter includes first and second capacitors. The AC signal is applied to the first capacitor, which includes first and second plates separated by a distance that depends on the root-mean-squared potential of the AC signal, but not on changes in the AC signal that occur over a time of 1/f. The second capacitor has first and second plates separated by a distance that depends on the separation of the first and second plates in the first capacitor. A detection circuit measures the capacitance of the second capacitor. The first plate of the first capacitor is preferably connected to the first plate of the second capacitor by a non-conducting mechanical link.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: October 12, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Chul Hong Park