Abstract: The present invention proposes a dynamic resources allocation method and system for guaranteeing tail latency SLO of latency-sensitive applications. A plurality of request queues is created in a storage server node of a distributed storage system with different types of requests located in different queues, and thread groups are allocated to the request queues according to logical thread resources of the service node and target tail latency requirements, and thread resources are dynamically allocated in real time, and the thread group of each request queue is bound to physical CPU resources of the storage server node. The client sends an application's requests to the storage server node; the storage server node stores the request in a request queue corresponding to its type, uses the thread group allocated for the current queue to process the application's requests, and sends responses to the client.

Abstract: Provided in the present invention are a K-Truss graph-based storage system cache prefetching method, a system, and a medium, where method steps of the present invention include: when a data request stream in a system arrives, an access mode of the data request stream is determined; if said mode is a sequence mode, then n sequence blocks after a data block corresponding to the data request stream are prefetched and serve as prefetch data; otherwise, the data block corresponding to the data request stream serves as a query vertex to query a K-Truss graph, a truss structure matching the query vertex is obtained, and data of a data block from within the truss structure is obtained and serves as prefetch data; the K-Truss graph is updated according to the data block corresponding to the data request stream; and lastly a prefetch data block is prefetched into a main memory.

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for memory mapping to enhance data cube performance. In some implementations, a system accesses a data set that includes data to be processed into a data cube. The system generates a memory-mapped data cube that includes a plurality of files including different segments of the data cube. Generating the memory-mapped data cube includes allocating memory-mapped buffers in non-volatile data storage and responding to subsequent memory allocation requests with addresses for the buffers such that components of the data cube are accumulated in the buffers. The memory-mapped data cube is loaded by storing the files of the data cube in disk-based storage, mapping the stored files of the data cube to virtual memory addresses, and caching portions of the data cube in random-access memory.

Abstract: A technique maintains online access to data stored in a plurality of storage devices during a hardware upgrade in which the plurality of storage devices moves between storage processor enclosures. The technique involves providing, from the plurality of storage devices, online access to the data while each storage device of the plurality of storage devices resides in a first storage processor enclosure. The technique further involves providing, from the plurality of storage devices, online access to the data while the plurality of storage devices is moved from the first storage processor enclosure to a second storage processor enclosure (e.g., transferring each storage devices one by one before triggering a rebuild process). The technique further involves providing, from the plurality of storage devices, online access to the data while each storage device of the plurality of storage devices resides in the second storage processor enclosure.

Abstract: Methods and systems are provided for configuring static memory in a device by analyzing a set of functionalities of a first device based on at least one use case wherein the at least one use case are associated with configuring available static memory in processing at least one functionality of the first device; configuring at least a first profile composed of the first part for memory allocation of the available static memory to a first processor, and a second part for memory allocation of the available static memory to a second processor of the first device; selecting the first profile either automatically or via a graphical user interface (GUI) by identifying a set of performance characteristics related to the functionality, and implementing the memory allocation by the first profile in processing the at least one functionality in the use case by the first device.

Abstract: A storage system comprises a plurality of storage devices, and is configured to establish a production drive group comprising a first subset of the storage devices, using a first firmware-level configuration process, and to establish a stealth drive group comprising a second subset of the storage devices, using a second firmware-level configuration process, the storage devices of the stealth drive group thereby being separated at a firmware level of the storage system from the storage devices of the production drive group. The storage system is further configured to copy data of one or more logical storage volumes from the production drive group to the stealth drive group, and responsive to completion of the copying of the data of the one or more logical storage volumes from the production drive group to the stealth drive group, to initiate a firmware-level reconfiguration process for the storage devices of the stealth drive group.

Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit includes a first interface coupled to a host device and a second interface coupled to the HBM device. The logic circuit receives a first command from the host device through the first interface and converts the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface. The first PIM command has a deterministic latency for completion. The logic circuit further receives a second command from the host device through the first interface and converting the received second command to a second PIM command that is sent to the HBM device through the second interface. The second PIM command has a non-deterministic latency for completion.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.

Abstract: Examples described herein relate to deletion of data entities in a deduplication system. Examples may maintain entries in a housekeeping queue, each entry including a priority value and a total unshared chunk size of a data entity to be deleted from the deduplication system. Examples may delete the data entities corresponding to the entries including a low priority value from the deduplication system. Examples may determine whether an available storage capacity of the deduplication system is sufficient after deleting the data entities corresponding to the entries including the low priority value. Examples may delete a data entity corresponding to an entry including a high priority value and a largest total unshared chunk size if the available storage capacity is insufficient.

Abstract: The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.

Abstract: Techniques are disclosed herein for improved copy data management functionality in storage systems. For example, a method receives copy usage data for one or more data copies associated with a storage array, wherein the copy usage data is indicative of a usage associated with each of the one or more data copies, and updates the one or more data copies with one or more usage tags based on the received copy usage data. Further, the method may then scan the one or more usage tags associated with each of the one or more data copies, select one or more storage tiers for at least a portion of the one or more data copies based on the scanning of the one or more usage tags, and cause at least a portion of the one or more data copies to be stored in the selected one or more storage tiers.

Abstract: Configuring systems to provide host access may include: configuring a stretched volume; and performing processing that allows the host access to the stretched volume. The processing may include: receiving a first command to create a first host object for access control for the host in the first data storage system; in response to receiving the first command, performing first processing including: creating the first host object that includes an initiator set of the host; and creating a second host object on the second data storage system, wherein the second host object includes the initiator set and specifies access control in the second data storage system for the host; receiving a second command to map the stretched volume to the first host object; and in response to receiving the second command, granting the host access to the stretched volume on the first data storage system and the second data storage system.

Abstract: Copying data from a source storage system to a target storage system includes resetting a write tracker on the source storage system to track writes to the source storage system by one or more host computing systems, copying data from the source storage system to the target storage system after resetting the write tracker, suspending writes to the source storage system after copying the data, and copying data portions of the source storage system to the target storage system that are indicated as being written by the write tracker after suspending writes to the source storage system. Applications that write data to the source storage system may be quiesced in connection with suspending writes to the source storage system. Data portions may be repeatedly copied from the source storage system to the target storage system until an end condition is reached.

Abstract: One or more aspects of the present disclosure relate to a storage health status. In embodiments, one or more events corresponding to a storage array can be received. Each event can include an alert. A type of each event can also be identified. For each event having a qualifying type, at least one prior event made obsolete by each received event can be cleared.

Abstract: Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.

Abstract: A volatile storage component operatively connected to a node, that includes a volatile storage device, a power source, and a plurality of processor cores, where, a first processor core of the plurality of processor cores is executing a volatile storage firmware, and a second processor core of the plurality of processor cores is executing a volatile storage operating system.

Abstract: Data traffic comprising data packets communicated between a memory sub-system and a host system is monitored by a processing device at the memory sub-system. Data packets are classified according to packet type. Log data comprising a frequency and latency information associated with each packet type is generated. The log data is stored in a memory component of the memory sub-system.