Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.

Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at least one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.

Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

Abstract: A storage system comprises a disk array enclosure comprising at least one enclosure controller, a plurality of data storage devices and at least one metadata storage device. The enclosure controller is configured to receive a write operation comprising data to be stored on at least one of the plurality of data storage devices and to determine a logical identifier for the data. The enclosure controller is further configured to determine a physical location on the at least one of the plurality of data storage devices for storing the data and to store the data at the physical location. The enclosure controller is further configured to update metadata stored on the at least one metadata storage device based at least in part on the physical location and the logical identifier and to return the logical identifier as a response to the received write operation.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

Abstract: A storage controller configures a plurality of logical volumes, a CDP meta volume that manages history information related to writing from a server system for the logical volumes, and a CDP data volume that stores data of the plurality of logical volumes. The storage controller searches for, if a restoration request including a restoration time is received, the restoration request having one of the plurality of volumes as a restoration target volume, history information of the restoration target volume from the CDP meta volume, copies, in a case in which an evacuation time of old data included in the searched history information of the restoration target volume is newer than the restoration time, an SEQ number of the searched history information as first restoration control information, and acquires old history information on the basis of a previous SEQ number of the restoration target volume from the CDP meta volume.

Abstract: Techniques are provided for computer memory mapping and allocation. In an example, a virtual memory address space is divided into an active half and a passive half. Processors make memory allocations to their respective portions of the active half until one processor has made a determined number of allocations. When that occurs, and when all memory in the passive half that has been allocated has been returned, then the active and passive halves are switched, and all processors are switched to making allocations in the newly-active half.

Abstract: A data storage device may include: a storage configured as a group of a plurality of memory blocks; and a controller configured to: control data input/output of the storage according to a request transferred from a host device; configure one or more first block groups by grouping a preset number of memory blocks which are selected at the same time among the memory blocks during an operation of the storage; configure one or more second block groups by replacing a bad memory block of the respective first block groups with a spare memory block; manage as a special block group a second block group where the spare memory block having replaced the bad memory block is not present in the same plane of the bad memory block, among the second block groups; and write data having a preset property to the special block group.

Abstract: A storage system is associated with at least one part of multiple storage devices in a resource pool, a part of a storage space in a storage device being inaccessible to the storage system. Techniques involve: identifying an extent within the part of the storage space in the storage device as a free extent; selecting a group of storage devices each with a free extent from the multiple storage devices in response to determining a virtual address range in the storage system as specified by an access request is inaccessible; mapping the virtual address range to a physical address range of the free extents in the group of storage devices; and allocating a storage space specified by the physical address range to the storage system. Therefore, the expansion of the resource pool can be implemented more conveniently and rapidly, and performance of the storage system can be improved.

Abstract: A method for dynamically altering a writes-per-day classification of multiple storage drives is disclosed. In one embodiment, such a method monitors, within a storage environment, an amount of overprovisioning utilized by multiple storage drives. Each storage drive has a writes-per-day classification associated therewith. Based on the amount of overprovisioning, the method periodically modifies the writes-per-day classification of the storage drives. The method then reorganizes the storage drives within various storage groups (e.g., RAID arrays, storage tiers, workloads, etc.) based on their writes-per-day classification. For example, the method may place, as much as possible, storage drives of the same writes-per-day classification within the same storage groups. A corresponding system and computer program product are also disclosed.

Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

Abstract: A method for retaining data pages in a cache is disclosed. In one embodiment, such a method stores multiple data pages in a cache. The method calculates, for each data page, a cost associated with promoting the data page from persistent storage media to the cache. The cost takes into account any data transformations (decryption, decompression, etc.) that are needed to promote the data page from the persistent storage media to the cache. In certain embodiments, the cost is represented as a score that is assigned to each data page. The method retains each data page in the cache for an amount of time that is related to its cost, such that data pages with a higher cost are retained in the cache longer than data pages with a lower cost. A corresponding apparatus and computer program product are also disclosed.

Abstract: A method including receiving, by a storage device, a write request, the write request associated with an amount of data sized in dependence upon information describing a layout of memory in the storage device. The method may also include writing, by the storage device, the data to a memory unit, the data written to a location within the memory unit in dependence upon the information.

Abstract: The present application is directed to a memory-access-multiplexing memory controller that can multiplex memory accesses from multiple hardware threads, cores, and processors according to externally specified policies or parameters, including policies or parameters set by management layers within a virtualized computer system. A memory-access-multiplexing memory controller provides, at the physical-hardware level, a basis for ensuring rational and policy-driven sharing of the memory-access resource among multiple hardware threads, cores, and/or processors.

Abstract: A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.

Abstract: The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

Abstract: The rate at which reads on a target memory portion initiate error recovery procedures can be monitored in real-time. Trigger rates can be used to perform analysis of a memory sub-system or to implement improvements in the memory sub-system. Trigger rate monitoring can include accessing a count of error recovery initializations for a target memory portion, wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-stage error recovery process was performed. Trigger rate monitoring can further include accessing a count of read operations corresponding to the target memory portion. The count of error recovery initializations and the count of read operations can be used to compute a trigger rate. The trigger rate, or multiple trigger rates from various times or from various target memory portions, can be used to compute a metric for the memory portion(s).

Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.

Abstract: A memory system includes a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded; and a memory controller suitable for scheduling an operation of the memory device with reference to the valid bits and the loading bits.