Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

Abstract: A method of packaging the silicon photonics wafer for fabricating custom optical-electrical modules includes fabricating a wafer with multiple dies of silicon photonics circuits based on custom design and conducting electrical and optical tests of the silicon photonics circuits in wafer level. The method further includes preparing the wafer for next point of use. Additionally, the method includes performing post-wafer processing on the wafer received at the next point of use. The method further includes conducting post-process electrical tests of the silicon photonics circuits in wafer level. Furthermore, the method includes preparing the wafer with known-good-dies or a known-good-wafer identified for custom use. Moreover, the method includes performing custom process on the know good dies.

Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.

Abstract: Disclosed are a laser bonding apparatus and a laser bonding method capable of bonding an electronic component to a three-dimensional structure having a regular or irregular shape in a curved portion such as an automobile tail lamp or a headlamp. The laser bonding apparatus and method for a three-dimensional structure may prevent misalignment and poor bonding of the electronic component with respect to the three-dimensional structure.

Abstract: A crystalline multilayer structure having a high-quality crystalline layer and a semiconductor device employing such a crystalline multilayer structure are provided. A crystalline multilayer structure, including a first crystalline layer having a first crystal, and a second crystalline layer stacked on the first crystalline layer and having a second crystal, wherein the first crystal includes polycrystalline ?-Ga2O3 and the second crystal is a single crystal of a crystalline oxide.

Abstract: A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties.

Abstract: A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member, the mounting member having a space between the first circuit member and the second circuit member; a step of preparing a laminate sheet including a first thermal-conductive layer and a second thermal-conductive layer, the first thermal-conductive layer disposed at least on one outermost side; a disposing step of disposing the laminate sheet on the mounting member such that the first thermal-conductive layer faces the second circuit members; and a sealing step of pressing the laminate sheet against the first circuit member and heating the laminate sheet, to seal the second circuit members so as to maintain the space, and to cure the laminate sheet.

Abstract: A method of processing a substrate includes forming a channel through a substrate, depositing a layer of polycrystalline silicon on sidewalls of the channel, and oxidizing uncovered surfaces of the polycrystalline silicon with an oxidation agent. The oxidizing agent causes formation of an oxidized layer, the oxidized layer having a uniform thickness on uncovered surfaces of the polycrystalline silicon. The method includes removing the oxidized layer from the channel with a removal agent, and repeating steps of oxidizing uncovered surfaces and removing the oxidized layer until removing a predetermined amount of the layer of polycrystalline silicon.

Abstract: In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.

Abstract: Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: Disclosed herein is an electronic component that includes a substrate, a functional layer formed on the substrate and having a plurality of alternately stacked conductor layers and insulating layers, and a plurality of terminal electrodes provided on an uppermost one of the insulating layers. The uppermost one of the insulating layers has a substantially rectangular planar shape and has a protruding part protruding in a planar direction from at least one side in a plan view.

Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.

Abstract: Wafer level encapsulated packages includes a wafer, a glass substrate hermetically sealed to the wafer, and an electronic component. The glass substrate includes a glass cladding layer fused to a glass core layer and a cavity formed in the glass substrate. The electronic component is encapsulated within the cavity. In various embodiments, the floor of the cavity is planar and substantially parallel to a plane defined by a top surface of the glass cladding layer. The glass cladding layer has a higher etch rate in an etchant than the glass core layer. In various embodiments, the wafer level encapsulated package is substantially optically transparent. Methods for forming the wafer level encapsulated package and electronic devices formed from the wafer level encapsulated package are also described.

Abstract: Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.

Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

Abstract: A laterally diffused metal oxide semiconductor device can include: a well region having a second doping type; a reduced surface field effect layer of a first doping type formed by an implantation process in a predetermined region of the well region, where a length of the reduced surface field effect layer is less than a length of the well region; a body region of the first doping type extending from a top surface of the well region into the well region; a drain portion of the second doping type extending from the top surface of the well region into the well region; and an insulating structure located between the body region and the drain portion, at least a portion of the insulating structure is located on the top surface of the well region.

Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.