Abstract: A metasurface unit cell for use in constructing a metasurface array is provided. The unit cell may include a ground plane layer comprising a first conductive material, and a phase change material layer operably coupled to the ground plane layer. The phase change material layer may include a phase change material configured to transition between an amorphous phase and a crystalline phase in response to a stimulus. The unit cell may further include a patterned element disposed adjacent to the phase change material layer and includes a second conductive material. In response to the phase change material transitioning from a first phase to a second phase, the metasurface unit cell may resonate to generate an electromagnetic signal having a defined wavelength. The first phase may be the amorphous phase or the crystalline phase and the second phase may be the other of the amorphous phase or the crystalline phase.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: In order to enable simple removal of a substrate used for manufacturing a semiconductor element, a manufacturing method includes forming a graphene layer on a substrate portion formed of a semiconductor, forming an element portion on the graphene layer, the element portion including a semiconductor layer directly formed on the graphene layer, which takes over crystal information relating to the substrate portion when the semiconductor layer is formed on the substrate portion without intermediation of the graphene layer, and performing cutting-off between the substrate portion and the element portion at the graphene layer.

Abstract: A mounting method is a method for mounting a diced semiconductor chip having a first face that is held on a carrier substrate and a second face that is an opposite face of the first face on a circuit board placed on a mounting table. The mounting method includes affixing the second face of the semiconductor chip to an adhesive sheet, removing the carrier substrate from the semiconductor chip, reducing an adhesive strength of the adhesive sheet, and mounting the semiconductor chip on the circuit board by holding a first face side of the semiconductor chip with a head to separate the semiconductor chip from the adhesive sheet, and joining a second face side of the semiconductor chip to the circuit board.

Abstract: The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45° and less than 135°.

Abstract: A display backplane includes a substrate, a thin film transistor over the substrate, and a pixel capacitor assembly over a side of the thin film transistor away from the substrate, and an orthographic projection of the pixel capacitor assembly on the substrate covers at least one portion of an orthographic projection of the thin film transistor on the substrate. The pixel capacitor assembly includes a first electrode, a passivation layer, and a second electrode, sequentially over a side of the thin film transistor away from the substrate, and an orthographic projection of the first electrode on the substrate is overlapped with the orthographic projection of the thin film transistor on the substrate. A display panel including the display backplane can further include an OLED component, arranged over a side of the pixel capacitor assembly away from the substrate.

Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.

Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to a first heat-conducting plate to be thermally coupled to a first heat source, a thermoelectric cooler (TEC) thermally coupled to the first plate, a second heat-conducting plate thermally coupled to the TEC and to be thermally coupled to a second heat source where the TEC is to at least partially thermally isolate the first plate from the second plate to reduce heat transfer from the first plate to the second plate.

Abstract: A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic element. The second protective layer covers the conductive wires, and the second protective layer has an opening corresponding to the ultrasonic element. The transmitting material contacts the ultrasonic element. The ASIC is connected to the wafer substrate, so that the via forms a space between the ASIC and the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protective layer, and the conducive pillar is respectively connected to the conductive wires and the soldering portion.

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: A method of frame handling during semiconductor package production includes: providing a lead frame having leads secured to a periphery of the lead frame by first tie bars; providing a multi-gauge spacer frame having spacers secured to a periphery of the spacer frame by second tie bars, the spacers being thicker than the second tie bars; and aligning the multi-gauge spacer frame with the lead frame such that the spacers and the second tie bars of the multi-gauge spacer frame do not contact the leads of the lead frame. A power semiconductor module and a method of assembling a power semiconductor module are also described.

Abstract: A film comprising a piezoelectric polymer has an upper surface and a lower surface. The film has an active region comprising the piezoelectric polymer, which extends from the upper surface of the film to the lower surface of the film. The film also comprises an adhesive sheet, which defines part of the upper or lower surface of the film. Circuit sheets may be bonded to the upper and lower surfaces in a lamination process to produce a laminated piezoelectric device.

Abstract: A semiconductor device includes an edge terminal structure portion provided between the active portion and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate, in which the edge terminal structure portion has a first high concentration region of the first conductivity type which has a donor concentration higher than a doping concentration of the bulk donor in a region between the upper surface and a lower surface of the semiconductor substrate, an upper surface of the first high concentration region is located on an upper surface side of the semiconductor substrate, and a lower surface of the first high concentration region is located on a lower surface side of the semiconductor substrate.

Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.

Abstract: The vibrator device includes: a base; a circuit element disposed on the base; a vibrating element disposed to at least partially overlap the circuit element in a plan view; and a support substrate that is disposed between the circuit element and the vibrating element and supports the vibrating element. In addition, the vibrating element has a frequency adjustment portion that performs frequency adjustment by removing at least a part of the vibrating element, and the support substrate includes a base portion that supports the vibrating element, a support portion that supports the base portion, a beam portion that couples the base portion the support portion, and a shielding portion that is connected to the beam portion, overlaps the frequency adjustment portion in a plan view, and has light shielding properties.

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.