Abstract: One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

Abstract: A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches.

Abstract: A part information restoration method is adapted to an electronic apparatus having first and second parts which are replaceable and are provided with a nonvolatile memory for storing part information unique to the part. The method includes storing, in a first nonvolatile memory of the first part, part information of the first part, and saving part information of the second part as a first reference information at least when replacing the second part, storing, in a second nonvolatile memory of the second part, the part information of the second part, and saving the part information of the first part as second reference information at least when replacing the first part. The method restores the first reference information in the second nonvolatile memory or restores the second reference information in the first nonvolatile memory, after replacing the first or second part.

Abstract: A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs.

Abstract: Method and apparatus for archiving de-duplicated data maintained by an intelligent backup appliance are described. In some examples, backup data managed by a backup appliance in a computer system is archived. A request to archive selected backup images of a plurality of backup images maintained by the backup appliance is received. The selected backup images are compared with a pool of de-duplicated data for the plurality of backup images maintained by the backup appliance to identify common data among the selected backup images and unique data in each of the selected backup images. A core backup is stored on first archive storage media, the core backup including at least a portion of the common data. A unique backup is stored on second archive storage media, the unique backup including the unique data a reference to the core backup stored on the first archive storage media.

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract: A data storage system including at least one storage controller having a first color policy and operative to store data onto a first data storage unit at a primary site as part of a current color of the primary site, at least one storage controller having a second color policy and operative to store data onto a second data storage unit at the primary site as part of the current color, and a color control node operative to provide each of the controllers with new color information while maintaining the integrity of dependent writes across color boundaries.

Abstract: Embodiments of archival storage system are disclosed. The archival storage system includes one or more removable disk drives that provide random access and are readily expandable. In embodiments, some or all of the data within the removable disk drive(s) is immutable. The archiving system creates a designation for the data representing the data as having Write Once Read Many (WORM) protection. Actions associated with the data may be received and determined to be read accesses. If the actions are something other than a read access, the archiving system, in embodiments, prevents the action on the data.

Abstract: The present invention is related with the management of memory in environments of limited resources, such as those found for example in a smart card. In a more particular manner, the invention relates to a method of managing the data storage resources of volatile memory, the object of which is to reduce the size of volatile memory necessary to implement the stack of the system, and thereby to reserve more volatile memory available for other needs or procedures of the system or of other applications When the stack grows and comes close to its established limit, the system carries out a transfer of a stack block located in the volatile memory to an area of non-volatile memory, hence this transfer allows a compression of the stack increasing its size in a virtual manner.

Abstract: This storage control apparatus 100 is able sufficiently to manifest the merits of economization of electrical power. The storage control apparatus 100 includes one or more additional storage units 150 which are adapted for the supply of power to them to be turned ON and OFF individually. Each of these additional storage units 150 includes a plurality of storage devices 154 (for example, a plurality of HDDs). When a user actuates a management device 106, and causes one or more RAID groups and a spare HDD for each of these RAID groups to be set within the storage control apparatus 100, an MPU 140 of the storage control apparatus 100 controls the management device 106 to make the user set each RAID group and the spare HDD for it within the same additional storage unit 150.

Abstract: The configuration of a copy pair is prevented in which data replication is conducted from a secondary system to a primary system and data is protected. A first storage device manages first information including a first measurement result related to a command received from a first host, and a second storage device manages second information including a second measurement result related to a command received from a second host. When a management computer makes an instruction to configure data replication from a first volume to a second volume, a storage system determines whether data replication from the first volume to the second volume or data replication from the second volume to the first volume is replication from the primary system to the secondary system based on the managed first information and second information, and the determined result is displayed on the management computer.

Abstract: A detachable storage device can comprise a memory, circuitry, and a user interface. The memory may comprise a storage partition. The circuitry may be configured to authorize access to the storage partition to a digital device when the detachable storage device is coupled to the digital device based, at least in part, on a user code. The user interface may be configured to receive the user code while the detachable storage device is within a detached state and provide the user code to the circuitry to allow access to the storage partition.

Abstract: A method for protecting data, adapted for a computer system, is provided. The computer system includes a storage device. The method includes: when the computer system executes a power-off procedure, inspecting whether a preset external storage device is connected to the computer system; if it is determined that the preset external storage device is connected to the computer system, when the computer system executes the power-off procedure, backing up data of a predetermined segment of the storage device to the preset external storage device, and generating a back-up data, and then writing a specific data template to the predetermined segment for covering original data of the predetermined segment.

Abstract: In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal.

Abstract: A technique for optimizing grace period detection in a uniprocessor environment. An update operation is performed on a data element that is shared with non-preemptible readers of the data element. A call is issued to a synchronous grace period detection method. The synchronous grace period detection method performs synchronous grace period detection and returns from the call if the data processing system implements a multi-processor environment at the time of the call. The synchronous grace period detection determines the end of a grace period in which the readers have passed through a quiescent state and cannot be maintaining references to the pre-update view of the shared data. The synchronous grace period detection method returns from the call without performing grace period detection if the data processing system implements a uniprocessor environment at the time of the call.

Abstract: A memory controller including a control unit for limiting the number of memory requests that are executed within a predetermined time period to regulate power consumption. The control unit may determine a memory request limit indicating the maximum number of memory requests that are allowed to be executed during the predetermined time period based on at least a carry-over limit and a new request limit. The carry-over limit may indicate the maximum number of carry-over memory requests that are allowed during the predetermined time period. The new request limit may indicate the maximum number of new memory requests that are allowed during the predetermined time period. The control unit may further control the number of memory requests that are executed in each of a sequence of predetermined time periods.

Abstract: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device.

Abstract: A data recording apparatus that writes data on/reads data from a hard disk drive in response to a data-write/read command received from an upper control device is provided. The data recording apparatus includes a command-aggregating device and a command-issuing device. The command-aggregating device is configured to generate an aggregate command by aggregating contents of a plurality of commands under the conditions that the plurality of commands are of the same kind continuously received from the control device and logical block addresses designated by the plurality of commands are consecutive addresses. The command-issuing device is configured to issue the aggregate command generated by aggregating the plurality of commands to a hard disk drive controller that controls the hard disk drive.

Abstract: Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.

Abstract: A method for accessing cells of a ring buffer by one or more writers, wherein the one or more writers are prevented from simultaneously accessing a cell of the ring buffer. In addition, a method for accessing cells of a ring buffer by one or more readers, wherein the one or more readers are prevented from simultaneously accessing a cell of the ring buffer.