Patents Examined by Eric Loonan
-
Patent number: 7640399Abstract: A system and method for managing a memory system. A system includes a plurality of processing entities and a cache which is shared by the processing entities. Responsive to a replacement event, circuitry may identify data entries of the shared cache which are candidates for replacement. Data entries which have been identified as candidates for replacement may be removed as candidates for replacement in response to detecting the data entry corresponds to data which is shared by at least two of the plurality of processing entities. The circuitry may maintain an indication as to which of the processing entities caused an initial allocation of data into the shared cache. When the circuitry detects that a particular data item is accessed by a processing entity other than a processing entity which caused an allocation of the given data item, the data item may be deemed classified as shared data.Type: GrantFiled: May 10, 2006Date of Patent: December 29, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Kevin M. Lepak, Roger D. Isaac
-
Patent number: 7636814Abstract: A system for asynchronous reads of old data blocks updated through a write-back cache includes a storage device, a write-back cache, a storage consumer, a storage processing node, and device management software. The device management software may be configured to store a new version of a data block in the write-back cache in response to an update request from the first storage consumer and to then send an update completion notification to the first storage consumer. Some time after the update completion notification has been sent, the device management software may be configured to send a previous version of the updated data block to the storage processing node, where it may be required to perform an operation such as a copy-on write operation or a snapshot update.Type: GrantFiled: April 28, 2005Date of Patent: December 22, 2009Assignee: Symantec Operating CorporationInventors: Ronald S. Karr, Craig Harmer
-
Patent number: 7627729Abstract: An apparatus, system, and method are disclosed for activating a synchronous mirror as a primary storage volume. The apparatus system and method include directing a third storage volume to store updates sent to the third storage volume from a second storage volume onto a first storage volume in response to the first storage volume becoming operational after a failure, terminating sending updates from the second storage volume to the third storage volume in response to the first storage volume becoming substantially consistent with the third storage volume, and synchronously storing updates received by the second storage volume on the first storage volume and asynchronously storing updates received by the first storage volume on the third storage volume in response to terminating sending updates from the second storage volume to the third storage volume after the first and third storage volumes are substantially consistent.Type: GrantFiled: September 7, 2006Date of Patent: December 1, 2009Assignee: International Business Machines CorporationInventors: Robert Francis Bartfai, Nicolas Marc Clayton, Shachar Fienblit, Olympia Gluck, Eli Malul, Gail Andrea Spear
-
Patent number: 7624228Abstract: A processing speed is improved when there is a pattern in which read requests making access to continuous areas in an LBA space repeatedly alternate with write requests making access to continuous or non-continuous areas in the LBA space. In one embodiment, when the pattern in which read requests making access to continuous areas in an LBA space repeatedly alternate with write requests making access to continuous or non-continuous areas in the LBA space is extracted or a notice that the pattern has occurred is given from a host, write data required by write requests is buffered while executing read requests, and when this buffering of the write data is started, the position at which write data is started to be written is set to a position where the capacity of the buffered write data maximizes, taking account of the ratio of the amount of data transferred to a cache memory during reading to the amount of data transferred to the cache memory during writing.Type: GrantFiled: June 28, 2006Date of Patent: November 24, 2009Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Yukie Hiratsuka, Manabu Nishikawa, Hiroaki Inoue
-
Patent number: 7606989Abstract: In a generational garbage collector, a decision is made to pre-tenure, or allocate new objects directly in the old generation, by a two step process. In the first step, during a young-generation collection, the number of bytes that survive collection is determined for each allocation site and a predetermined number of sites with the highest number of surviving bytes are selected as candidate sites. In the second step, during a subsequent young-generation collection, the survival rates are determined for the candidate sites and objects to be allocated from sites with a sufficiently high survival rate are allocated directly in older generations.Type: GrantFiled: September 1, 2005Date of Patent: October 20, 2009Assignee: Sun Microsystems, Inc.Inventors: David L. Detlefs, Antonios Printezis, Fabio Rojas
-
Patent number: 7603522Abstract: A system and method for managing a cache subsystem. A system comprises a plurality of processing entities, a cache shared by the plurality of processing entities, and circuitry configured to manage allocations of data into the cache. Cache controller circuitry is configured to allocate data in the cache at a less favorable position in the replacement stack in response to determining a processing entity which corresponds to the allocated data has relatively poor cache behavior compared to other processing entities. The circuitry is configured to track a relative hit rate for each processing entity, such as a thread or processor core. A figure of merit may be determined for each processing entity which reflects how well a corresponding processing entity is behaving with respect to the cache. Processing entities which have a relatively low figure of merit may have their data allocated in the shared cache at a lower level in the cache replacement stack.Type: GrantFiled: May 10, 2006Date of Patent: October 13, 2009Assignee: Globalfoundries Inc.Inventors: Kevin M. Lepak, Roger D. Isaac
-
Patent number: 7596667Abstract: In a computer system having a multithreaded application and a generational garbage collector that dynamically pre-tenures objects from a predetermined number of candidate allocation sites, allocated byte accounting is performed by each application thread using an array that contains a number of entries equal to the total number of candidate sites at any given time. Each array is indexed by a site number assigned to that site and contains a bytes allocated count for that site. At compilation time, object allocation code that is generated by the compiler is modified to update an array entry associated with a site number that is assigned when the site is selected as a candidate site. Since each array is local to the thread that contains it, each thread can write into its array without using atomic operations or locks.Type: GrantFiled: September 1, 2005Date of Patent: September 29, 2009Assignee: Sun Microsystems, Inc.Inventors: David L. Detlefs, Antonios Printezis, Fabio Rojas
-
Patent number: 7584323Abstract: Provided is a method of generating and searching for a single ternary content addressable memory (TCAM) entry for range search and exact-match search. First, it is determined whether an entry to be added is a range search entry or an exact-match search entry. When the entry is the range search entry, a bit at a predetermined position in the upper m bits corresponding to a range represented by the entry is set to “1” and the remaining bits including lower n bits is set to a “don't care” bit x, based on a range table for representing position information of one of the upper m bits which is set to “1” in ranges. When the entry is the exact-match search entry, the upper m bits is set to “don't care” bit x and the lower n bits is set to the entry value. By generating and searching for a single TCAM entry for a range search and an exact-match search, a space for storing the TCAM entry can be optimized and efficiency thereof can be improved.Type: GrantFiled: October 18, 2006Date of Patent: September 1, 2009Assignee: Electronic and Telecommunications Research InstituteInventors: Young Ho Kim, Bo Heung Chung, Jae Deok Lim, Seung Ho Ryu, Yong Sung Jeon, Sang Woo Lee, Ki Young Kim
-
Patent number: 7565489Abstract: The present invention extends to methods, systems, and computer program products for identifying relevant information to cache. A computer system accesses a marked data entity that has been marked for caching at a client computer system. The marked data entry is marked for caching based on the relevance of the marked data entity from the perspective of a requested data entity. The computer system identifies relationships from the marked data entity to one or more other data entities. The computer system selects, from among the identified relationships, any relationships that satisfy a relevance threshold from the perspective of the requested data entity. The computer system identifies, from among the one or more other data entities, any of the other data entities that correspond to a selected relationship satisfying the relevance threshold. The computer system marks the identified other data entities for caching.Type: GrantFiled: July 1, 2005Date of Patent: July 21, 2009Assignee: Microsoft CorporationInventors: Maarten Willem Mullender, Ricard Roma i Dalfó
-
Patent number: 7546426Abstract: A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs.Type: GrantFiled: December 21, 2006Date of Patent: June 9, 2009Assignee: Hitachi, Ltd.Inventors: Kentaro Shimada, Akiyoshi Hashimoto
-
Patent number: 7543105Abstract: A memory access control system is provided which includes a memory master to make a request for access to memory, a memory control section to produce control signals of memories based on access information and a high predicting section to predict whether the next access to each bank in memory is obtained to a same page (hit is found) wherein the memory control section, when the hit predicting section predicts that a hit is found, terminates its routine without closing the bank being presently accessed at time of completion of present access operations and, when the hit predicting section predicts that a miss is found, closes a bank being presently accessed and terminates its routine.Type: GrantFiled: March 26, 2004Date of Patent: June 2, 2009Assignee: NEC CorporationInventor: Tetsuro Takizawa
-
Patent number: 7539826Abstract: By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.Type: GrantFiled: April 29, 2005Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Moo-Sung Chae, Kye-Hyun Kyung
-
Patent number: 7533229Abstract: One or more computer systems, a carrier medium, and a method are provided for backing up virtual machines. The backup may occur, e.g., to a backup medium or to a disaster recovery site, in various embodiments. In one embodiment, an apparatus includes a computer system configured to execute at least a first virtual machine, wherein the computer system is configured to: (i) capture a state of the first virtual machine, the state corresponding to a point in time in the execution of the first virtual machine; and (ii) copy at least a portion of the state to a destination separate from a storage device to which the first virtual machine is suspendable. A carrier medium may include instructions which, when executed, cause the above operation on the computer system. The method may comprise the above highlighted operations.Type: GrantFiled: June 12, 2006Date of Patent: May 12, 2009Assignee: Symantec Operating CorporationInventor: Hans F. van Rietschote
-
Patent number: 7529903Abstract: Systems, methods and media for performing auto-migration of data among a plurality of memory devices are disclosed. In one embodiment, memory access of application program data is monitored for each of one or more application programs. The data may be stored in one or more of a plurality of memory storage devices, each with its own performance characteristics. Monitored access is evaluated to determine an optimal distribution of the application programs data, typically stored in files, among the plurality of memory storage devices. The evaluation takes into account service level requirements of each application program. Periodically, data may be automatically transferred from one memory storage device to another to achieve the determined optimal allocation among the available memory storage devices consistent with service level requirements.Type: GrantFiled: July 5, 2005Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Gregory Jensen Boss, Christopher James Dawson, Rick Allen Hamilton, II, Timothy Moffett Waters
-
Patent number: 7526625Abstract: A semiconductor memory card that has a sufficient storage capacity when an EC application writes data to a storage is provided. A usage area for the EC application in an EPPROM 3 in a TRM 1 is expanded. The expansion is such that a partition generated in a flash memory 2 outside the TRM 1 is assigned to the EC application while a partition table is allocated in the internal EEPROM 3. Because the partition table is in the TRM 1, only a CPU 7 in the TRM 1 is able to access the generated partition table. Secrecy of stored contents increases because the access to the expanded area is limited to the CPU 7 in the TRM 1.Type: GrantFiled: January 30, 2004Date of Patent: April 28, 2009Assignee: Panasonic CorporationInventors: Hiromi Ebara, Shinji Kawano, Futoshi Nakabe
-
Patent number: 7516277Abstract: A system and method to monitor caches of at least one Java virtual machine (“JVM”). A program is operated on the at least one JVM. Objects associated with the program are cached within a local cache of the JVM. Cache status information about the local cache is generated and then the cache status information is reported into memory external to the JVM to enable monitoring of the local cache from external to the JVM.Type: GrantFiled: April 28, 2005Date of Patent: April 7, 2009Assignee: SAP AGInventors: Frank Kilian, Christian Fleischer, Petio Petev
-
Patent number: 7516266Abstract: A system capable of sequentially writing data to a flash memory. The system includes at least one virtual block, at least one physical block, and at least one active block. Each virtual block has a plurality of virtual pages and a virtual block address. Each virtual page has a virtual page offset. Each physical block has a plurality of physical pages and a physical block address. Each physical page of the physical block has a physical page offset. Each active block has a plurality of physical pages and an active block address. Each physical page of the active block has a physical page offset. Each virtual block is mapped to one physical block. In the mapped virtual and physical blocks, each virtual page is mapped to one physical page. In the mapped virtual and physical pages, the virtual page offset is the same as the physical page offset.Type: GrantFiled: April 28, 2005Date of Patent: April 7, 2009Assignee: Mediatek IncorporationInventor: Hung-Shiun Fu
-
Patent number: 7502897Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a block of instructions is received for execution as an object in a software transactional memory transaction. The base of the object is computed, a lock is found for the object using the base of the object.Type: GrantFiled: June 28, 2006Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adl-Tabatabai
-
Patent number: 7502900Abstract: A data processing integrated circuit comprises a CPU, a memory that stores a program for controlling the CPU, a memory transfer controller for sending/receiving data to/from an external memory provided external to the data processing integrated circuit, and a read address storing section into which an address of data in the external memory is set by the CPU controlled by the program stored in the memory, which data is to be used at a later stage than a process being executed by the CPU, wherein the memory transfer controller transfers the data stored at the address in the external memory to the memory.Type: GrantFiled: December 23, 2005Date of Patent: March 10, 2009Assignee: Sanyo Electric Co., Ltd.Inventor: Iwao Honda
-
Patent number: 7496710Abstract: It has been discovered that preventing performance of ineffective write operations reduces demand on memory bandwidth, as well as preventing unnecessary consumption of resources. A write operation is inspected to determine whether the write operation will effectively modify the destination of the write operation (i.e., whether a net change will occur). Those ineffective write operations are not performed. Preventing performance of the write operation includes not changing contents of locations in a memory hierarchy that correspond to the destination of the write operation.Type: GrantFiled: April 1, 2005Date of Patent: February 24, 2009Assignee: Sun Microsystems, Inc.Inventor: Balakrishna Venkatrao