Abstract: A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) incorporate a constraint that reduces/eliminates command collisions, data conflicts, and/or the need to check particular timing parameters, or 3) a combination of both. The memory controller design tool may work in conjunction with a memory controller designer to define and use the constraints.
Type:
Grant
Filed:
April 7, 2005
Date of Patent:
February 10, 2009
Assignee:
International Business Machines Corporation
Inventors:
Mark David Bellows, Ryan Abel Heckendorf
Abstract: A microcomputer with built-in flash memory to which data can be written using a write clock signal, comprises a fixed oscillator circuit which outputs a clock signal of fixed frequency for generating the write clock signal. The flash memory is designed with a write-disturb time such that data loss does not occur when writing data with the write clock signal of fixed frequency.
Abstract: An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter respectively, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address.
Abstract: The present invention provides a data recording device which starts recording data a to a memory A when a command is given to start recording data. When the remaining capacity of the memory A is not greater than a given capacity value x, data recording to the memory A is concurrent with data recording to a memory B. When the capacity of the memory A is full, recording data x to the memory A is ceased. Thereafter, when a command is given to cease an operation for recording data to the memory B, an inquiry is made as to whether space capacity of the memory B is greater than an amount of data a of the memory A. Only when the inquiry is answered in the affirmative, the data a recorded on the memory A is copied to the memory B.
Type:
Grant
Filed:
April 4, 2005
Date of Patent:
July 17, 2007
Assignees:
Sanyo Electric Co., Ltd., Sanyo Technosound Co., Ltd.