Patents Examined by Eric S Cardwell
  • Patent number: 9772950
    Abstract: Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: September 26, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9747211
    Abstract: A cache memory includes: a tag storage section in which one of a plurality of indexes, each index containing a plurality of tag addresses and one suspension-indicating section, is looked up by a first address portion of an accessed address; a data storage section; a tag control section configured to, when the suspension-indicating section contained in the looked-up index indicates suspension, allow access relevant to the accessed address to wait, and when the suspension-indicating section contained in the looked-up index indicates non-suspension, compare a second address portion different from the first address portion of the accessed address to each of the plurality of tag addresses contained in the looked-up index, and detects a tag address matched with the second address portion; and a data control section.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 29, 2017
    Assignee: SONY CORPORATION
    Inventor: Taichi Hirao
  • Patent number: 9733867
    Abstract: A storage administrator may maintain location information in separate layers. A data storage system may identify the location of particular data by identifying the virtual location of data, such as the logical extent to which the data belongs. Object stores may maintain mappings of virtual locations to physical locations, such as mappings of extent identifiers to virtual storage objects and mappings of virtual storage objects to storage unit locations. When particular data is relocated to a new location, a storage administrator may update mappings used to translate virtual locations to physical locations, such as an extent-object mapping or an object-storage unit mapping. References to the virtual locations, such as references to logical extent identifiers, may not be updated in response to the relocation of data.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 15, 2017
    Assignee: Bracket Computing, Inc.
    Inventors: Jason A. Lango, John K. Edwards, Nitin Muppalaneni
  • Patent number: 9733833
    Abstract: Provided are a computer program product, system, and method for selecting pages implementing leaf nodes and internal nodes of a data set index for reuse in memory. Pages in the memory are allocated to internal nodes and leaf nodes of a tree data structure representing all or a portion of a data set index for the data set. At least at least one duration parameter indicates an amount of time after which an unused page implement one of the internal nodes or leaf nodes is eligible for reuse. Selection is made of at least one selected page allocated to at least one of the leaf nodes and the internal nodes that has not been used for one of the at least one duration parameter for reuse.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek L. Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
  • Patent number: 9727468
    Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Yen-Cheng Liu, George Cai, Jeffrey D. Gilbert
  • Patent number: 9720620
    Abstract: A block-based storage system may implement efficient replication for restoring a data volume from a reduced durability state. A storage node that is not replicating write requests for a data volume may determine that replication for the data volume is to be enabled. A peer storage node may be identified that maintains a stale replica of the data volume. One or more replication operations may be performed to update stale data chunks in the stale replica of the data volume with current data chunks without updating data chunks in the stale replica of the data volume that are current. Stale replicas that are no longer needed may be deleted according timeouts or the amount of stale data in the replica.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 1, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Danny Wei, Kerry Quintin Lee, John Luther Guthrie, II, Jianhua Fan, James Michael Thompson, Nandakumar Gopalakrishnan
  • Patent number: 9710166
    Abstract: Systems and methods for predicting the compressibility of data in a flash storage device are provided. One such method involves extracting byte intervals from the block of data, each of the byte intervals consisting of a preselected number of bytes, performing a hash function to map the byte intervals into a plurality of bins, the plurality of bins comprising one bin for each possible value of the byte intervals, incrementing a hit count each time more than one of the byte intervals is mapped into a single bin of the plurality of bins, and determining whether to compress the block of data based on a comparison of a ratio of the hit count to a total number of the byte intervals and a preselected threshold. This method may be implemented in hardware to ensure fast and efficient execution.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 18, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Wei Huang, Sanjay Ramakrishna Pillay, Sanjay Subbarao
  • Patent number: 9690713
    Abstract: Various systems and methods to use a plurality of linked lists for keeping track of changes to be made in data sets currently in a flash memory. To enhance efficiency of the system, the changes to be made in any particular data set are aggregated in a random access memory (“RAM”) until a sufficient volume of changes have been aggregated to justify a rewrite of the flash memory block in which the particular data set is stored. Since a flash memory may have millions of memory blocks and data sets, there are potentially tremendous demands on the memory resources of the RAM to keep track of all the changes, but the problem presented by these potential demands is avoided through the use of linked lists, in which each list links all of the changes that have been aggregated in RAM and that apply to one specific data set.
    Type: Grant
    Filed: April 19, 2015
    Date of Patent: June 27, 2017
    Assignee: Parallel Machines Ltd.
    Inventors: Lior Khermosh, Ofer Bar-Or, Gal Zuckerman
  • Patent number: 9658798
    Abstract: For performing efficient full-stride copy source-to-target operations in a computing storage environment by a processor device, pursuant to a destage operation, a determination is made whether to destage a full stride or one track of data on a target volume by comparing a counted number of modified tracks for the full stride against a predetermined threshold.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Lokesh M. Gupta, Theodore T. Harris, Jr., Suguang Li
  • Patent number: 9658957
    Abstract: Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 23, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Vikram Joshi, Yang Luan, Manish R. Apte, Hrishikesh A. Vidwans, Michael F. Brown
  • Patent number: 9658802
    Abstract: According to one embodiment, a storage system includes a plurality of memory nodes that are connected to each other in two or more different directions and a connection unit. The connection unit issues a command in response to a request from the outside. In the storage system, a plurality of logical memory nodes are constructed by allocating, to one logical memory node, memory nodes including at least one first memory node which stores data to be accessed by the command and a second memory node which stores redundant data of the data stored in the first memory node. The command includes a first address which designates one of the plurality of logical memory nodes and a second address which designates a storage position in a memory space allocated to each logical memory node.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Kurita, Daisuke Hashimoto
  • Patent number: 9653171
    Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Michael Abraham, Tomoharu Tanaka, Koichi Kawai, Yuichi Einaga
  • Patent number: 9632726
    Abstract: A modular system including a set of functionality tiles and a control tile storing a storage structure, an initialization file, and operation instructions. The method for operating a custom device made using the modular system includes: sending operation settings for each tile to the respective tile upon device initialization; operating each tile based on the operation settings; writing the output from each tile to the storage structure; monitoring data streams within the storage structure for a trigger event; reading data off the storage structure in response to occurrence of the trigger event; and processing the read data according to a processing function specified by the operation instructions.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: April 25, 2017
    Assignee: Arch Systems Inc.
    Inventor: Timothy Matthew Burke
  • Patent number: 9632843
    Abstract: A method and system for allocating memory in a RAID system. A RAID system requires the use of shared memory to store processed data related to operations of different mass storage devices. Certain RAID algorithms require different sizes of memory regions of the memory, and multiple requests to lock the required memory regions are therefore required. As multiple requests are made in parallel for different operations, the multiple requests for each operation are sorted in a predetermined order. This ensures that all memory regions for one operation can be locked. Requests for memory regions locked by a second operation are held in a pending state to wait for release of those memory regions by a first operation, at which point they are locked again by the second operation.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: April 25, 2017
    Assignee: Microsemi Storage Solutions (U.S.), Inc.
    Inventors: Jesslly Wong, Raymond Lam, Tao Zhong
  • Patent number: 9626301
    Abstract: Embodiments are disclosed for implementing a priority queue in a storage device, e.g., a solid state drive. At least some of the embodiments can use an in-memory set of blocks to store items until the block is full, and commit the full block to the storage device. Upon storing a full block, a block having a lowest priority can be deleted. An index storing correspondences between items and blocks can be used to update priorities and indicated deleted items. By using the in-memory blocks and index, operations transmitted to the storage device can be reduced.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 18, 2017
    Assignee: Facebook, Inc.
    Inventors: Wyatt Andrew Lloyd, Linpeng Tang, Qi Huang
  • Patent number: 9619395
    Abstract: An information processing device includes a main control circuit including a central arithmetic processor that executes first processing through a first program, a sub-control circuit that executes second processing independently of the first processing, a primary storage circuit, and a secondary storage circuit. The secondary storage circuit has a slower access speed than the primary storage circuit. The secondary storage circuit stores a second program used for third processing executed once the first processing and the second processing are both complete. The main control circuit further includes a cache memory having a faster access speed than the secondary storage circuit and a cache controller. In a situation in which the second processing is not yet complete at a completion time of the first processing, the cache controller executes pre-reading of the second program from the secondary storage circuit and stores the second program into the cache memory.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 11, 2017
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Satoshi Goshima
  • Patent number: 9607664
    Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
  • Patent number: 9600203
    Abstract: A block-based storage system may implement reducing durability state for a data volume. A determination may be made that storage node replicating write requests for a data volume is unavailable. In response, subsequent write requests may be processed according to a reduced durability state for the data volume such that replication for the data volume may be disabled for the storage node. Write requests may then be completed at a fewer number of storage nodes prior to acknowledging the write request as complete. Durability state for the data volume may be increase in various embodiments. A storage node may be identified and replication operations may be performed to synchronize the current data volume at the storage node with a replica of the data volume maintained at the identified storage node.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Danny Wei, Kerry Quintin Lee, James Michael Thompson, John Luther Guthrie, II, Jianhua Fan, Nandakumar Gopalakrishnan
  • Patent number: 9588889
    Abstract: Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories. Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: March 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Simon C. Steely, Jr., William C. Hasenplaugh, Joel S. Emer
  • Patent number: 9588567
    Abstract: A control apparatus that causes data in a first storage unit to be written in a second storage unit, with power supplied from a sub power supply, when supply of power from a main power supply is discontinued, the control apparatus includes a remaining feed duration obtaining unit that obtains remaining feed duration during which the sub power supply can supply the power; and a retry count setting unit that sets a maximum retry count for writing the data from the first storage unit to the second storage unit, based on the remaining feed duration obtained by the remaining feed duration obtaining unit, when an error occurs while the data is being written.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yoko Kawano, Terumasa Haneda, Atsushi Uchida, Toshihiro Tomozaki