Patents Examined by Erik T. K. Peterson
  • Patent number: 11930681
    Abstract: A display panel and a display device are provided. The display panel includes a first color sub-pixels and a second color sub-pixel. The first color sub-pixel includes a first effective light emitting region, the second color sub-pixel includes a second effective light emitting region, an area of the second effective light emitting region is smaller than that of the first effective light emitting region. The first color sub-pixel includes a first color light emitting layer, the second color sub-pixel includes a second color light emitting layer, an area ratio between orthographic projections of the first color light emitting layer and the first effective light emitting region on the base substrate is less than an area ratio between orthographic projections of the second color light emitting layer and the second effective light emitting region on the base substrate.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 12, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongli Wang, Chang Luo, Lei Chen, Kening Zheng, Chen Xu
  • Patent number: 11908970
    Abstract: A process for manufacturing a multilayered thin film, includes: forming a photovoltaic conversion layer, comprising Cu2O as a main component, on a first transparent electrode; and placing, under a first atmosphere at an oxygen level of from 5.0×10?8 [g/L] to 5.0×10?5 [g/L] for 1 h to 1600 h, a member having the photovoltaic conversion layer formed on the first transparent electrode.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 20, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Yuya Honishi, Soichiro Shibasaki, Naoyuki Nakagawa, Mutsuki Yamazaki, Yoshiko Hiraoka, Kazushige Yamamoto
  • Patent number: 11894271
    Abstract: A method of processing a wafer includes a wafer preparing step of preparing a measurement wafer and a product wafer, a measurement etching step of supplying a gas in a plasma state to first areas of the measurement wafer that correspond to streets thereon to form grooves in the measurement wafer, a measuring step of demarcating a plurality of concentric areas in an array from a center to an outer circumference of the measurement wafer, and measuring depths of the grooves in the respective concentric areas, a thickness adjusting step of adjusting a thickness of the product wafer such that the product wafer is progressively thinner in areas thereof that correspond to the areas of the measurement wafer where the grooves are shallower, and an etching step of supplying a gas in a plasma state to second areas of the product wafer that correspond to streets thereon.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: February 6, 2024
    Assignee: DISCO CORPORATION
    Inventors: Karl Heinz Priewasser, Hideyuki Sandoh
  • Patent number: 11882682
    Abstract: Embodiments relate to a method for manufacturing a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate in which a plurality of contact pads arranged in an array are provided, wherein the contact pad protrudes from the upper surface of the substrate; forming a first barrier layer on the substrate and the surface of the contact pad; forming a first conductive layer on the surface of the first barrier layer; etching the upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downward to the substrate, the projection of the first recessed structure on the substrate surrounds the contact pad, and the second recessed structure is formed in the first conductive layer and arranged above each of the corresponding contact pads.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jiancheng Hu
  • Patent number: 11871571
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: January 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 11854888
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 26, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, Karthik Balakrishnan, James S. Papanu, Wei-Sheng Lei
  • Patent number: 11837589
    Abstract: A tiled display device including a first display device; a second display device located at one side of the first display device in a first direction; a first chassis disposed under the first display device to support the first display device; and a second chassis disposed under the second display device to support the second display device. An end portion of the first chassis and an end portion of the second chassis are directly connected to each other, and an end portion of the first display device and an end portion of the second display device come into direct contact with each other.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Woo Lim, Hyung June Kim, Eun Je Jang, Jang Bog Ju
  • Patent number: 11817422
    Abstract: A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.
    Type: Grant
    Filed: November 9, 2019
    Date of Patent: November 14, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yohei Igarashi
  • Patent number: 11791212
    Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Brandon P. Wirz
  • Patent number: 11793047
    Abstract: Provided is a display panel including a display area including a first pixel region in which a plurality of pixels are disposed and an image-capturing area including a second pixel region in which a plurality of pixel groups are disposed and a plurality of light-transmitting portions are disposed between the pixel groups. The light-transmitting portions are disposed along virtual spiral reference lines which spirally extend outward from the center of the image-capturing area, and sizes of the light-transmitting portions increase as a distance from the center of the image-capturing area increases.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: October 17, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Duk Young Jeong
  • Patent number: 11793054
    Abstract: A display device includes a protective layer. A display panel is disposed on an upper surface of the protective layer. The display panel includes a display area configured to display an image and a non-display area at least partially surrounding the display area. A cover panel is disposed on a back surface of the protective layer. The cover panel includes an opening that exposes the protective layer. A fingerprint sensor is disposed within the opening of the cover panel. The fingerprint sensor is configured to sense a fingerprint. A first fixing member is disposed on one surface of the fingerprint sensor. A second fixing member at least partially overlaps at least one side of the first fixing member, the second fixing member fixing the fingerprint sensor. The first fixing member and the second fixing member each include at least one different material from each other.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hye Sung Kim, Sung Wook We
  • Patent number: 11772961
    Abstract: A microelectromechanical systems (MEMS) die includes a first diaphragm and a second diaphragm, wherein the first diaphragm and the second diaphragm bound a sealed chamber. A stationary electrode is disposed within the sealed chamber between the first diaphragm and the second diaphragm. A tunnel passes through the first diaphragm and the second diaphragm without passing through the stationary electrode, wherein the tunnel is sealed off from the chamber. The MEMS die further includes a substrate having an opening formed therethrough, wherein the tunnel provides fluid communication from the opening, through the second diaphragm, and through the first diaphragm.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: October 3, 2023
    Assignee: KNOWLES ELECTRONICS, LLC
    Inventors: Michael Kuntzman, Ken Deng, Faisal Zaman, Bing Yu, Vahid Naderyan, Peter V. Loeppert
  • Patent number: 11769675
    Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 26, 2023
    Inventors: Gautham Ragunathan, David Tossell, Oliver Ansell
  • Patent number: 11721788
    Abstract: A method according to embodiments of the invention includes providing a wafer of semiconductor devices grown on a growth substrate. The wafer of semiconductor devices has a first surface and a second surface opposite the first surface. The second surface is a surface of the growth substrate. The method further includes bonding the first surface to a first wafer and bonding the second surface to a second wafer. In some embodiments, the first and second wafer each have a different coefficient of thermal expansion than the growth substrate. In some embodiments, the second wafer may compensate for stress introduced to the wafer of semiconductor devices by the first wafer.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 8, 2023
    Assignee: Lumileds LLC
    Inventors: Quanbo Zou, Salman Akram, Jerome Chandra Bhat
  • Patent number: 11716877
    Abstract: An organic light-emitting display device and a method of manufacturing the same are disclosed and these improve electrical connection between a cathode and an auxiliary electrode in order to reduce the resistance of the cathode that covers a plurality of sub-pixels, and may prevent lateral current leakage using the same structure.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 1, 2023
    Assignee: LG Display Co., Ltd.
    Inventor: Joon-Young Heo
  • Patent number: 11682569
    Abstract: A workpiece cutting method of cutting a workpiece along a plurality of crossing division lines formed on a front side of the workpiece, by using a cutting blade having a thickness gradually decreasing toward an outer circumference of the cutting blade. The workpiece cutting method includes a shape checking step of checking a shape of the cutting blade; a cut depth setting step of setting a cut depth by the cutting blade into the workpiece according to the shape checked in the shape checking step such that a width of a cut groove to be formed on the front side of the workpiece becomes a previously set value; and a cutting step of cutting the workpiece with the cut depth set in the cut depth setting step, by forcing the cutting blade into the workpiece from the front side thereof.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 20, 2023
    Assignee: DISCO CORPORATION
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 11677049
    Abstract: An optoelectronic device, including: light-emitting sources, each light-emitting source being capable of emitting a first radiation at a first wavelength; photoluminescent blocks distributed into first photo-luminescent blocks capable of converting by optical pumping the first radiation into a second radiation at a second wavelength and second photoluminescent blocks capable of converting by optical pumping the first radiation into a third radiation at a third wavelength; and for each photoluminescent block, an optical coupler including a first photonic crystal at least partially surrounding the photoluminescent block and covering, with the photo-luminescent block, one of the light-emitting sources next to the photoluminescent block, the optical coupler being capable of modifying the propagation direction of rays of the first radiation emitted by the light-emitting source to redirect the rays towards the photoluminescent block.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 13, 2023
    Assignee: Aledia
    Inventor: Tiphaine Dupont
  • Patent number: 11651997
    Abstract: A recognition method of a kerf includes a bonding step of bonding a workpiece to a dicing tape greater in size than the workpiece, a pre-machining imaging step of imaging an optimal region of the dicing tape where the workpiece is not bonded, a kerf forming step of forming a kerf in the optimal region by a cutting machine, a post-machining imaging step of imaging the optimal region with the kerf formed therein, and a recognition step of comparing intensities of light received at each two corresponding pixels in respective images of the optimal region as acquired by the pre-machining imaging step and the post-machining imaging step, subtracting the each two pixels where intensities of received light are the same, and recognizing as the kerf a region formed by the remaining pixels.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 16, 2023
    Assignee: DISCO CORPORATION
    Inventor: Satoshi Miyata
  • Patent number: 11631652
    Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ying-Jui Huang, Ching-Hua Hsieh, Chien-Ling Hwang, Chia-Sheng Huang
  • Patent number: 11600530
    Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yi Lee, Hong-Hsien Ke, Chung-Ting Ko, Chia-Hui Lin, Jr-Hung Li