Abstract: A light emitting device including a first light emitting part, a second light emitting part disposed over the first light emitting part, a third light emitting part disposed over the second light emitting part, a passivation layer surrounding outer sidewalls of the first, second, and third light emitting parts, a via pattern electrically coupled with at least one of the first, second, and third light emitting parts, and passing through at least a part of one of the first, second, and third light emitting parts, and a pad electrically coupled with the via pattern and overlapping the passivation layer.

Abstract: An embedding method includes: removing a metal oxide film at a surface of a metal layer from a substrate that includes the metal layer on a bottom of a recess formed in an insulating layer; covering the surface of the metal layer by embedding ruthenium in the recess from the bottom of the recess; forming a ruthenium liner film in the recess; and further embedding ruthenium in the recess in which the liner film is formed.

Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: A method of manufacturing a nitride semiconductor light-emitting element includes: growing an n-side superlattice layer that includes InGaN layers and GaN layers; and, after the step of growing the n-side superlattice layer, growing a light-emitting layer. The step of growing the n-side superlattice layer comprises repeating a cycle n times (n is a number of repetition), the cycle including growing one InGaN layer and growing one GaN layer. In the step of growing the n-side superlattice layer, the step of growing one GaN layer in each cycle from a first cycle to an mth cycle is performed using carrier gas that contains N2 gas and does not contain H2 gas. The step of growing one GaN layer in each cycle from a (m+1)th cycle to an nth cycle is performed using gas containing H2 gas as the carrier gas.

Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

Abstract: An imaging device includes: a semiconductor substrate including a first diffusion region of a first conductivity type and a second diffusion region of the first conductivity type; a first plug that is connected to the first diffusion region and that contains a semiconductor; a second plug that is connected to the second diffusion region and that contains a semiconductor; and a photoelectric converter that is electrically connected to the first plug. An area of the second plug is larger than an area of the first plug in a plan view.

Abstract: A method of manufacturing a nitride semiconductor light-emitting element includes growing an n-side semiconductor layer, an active layer, and a p-side semiconductor layer. The step of growing the active layer includes growing a first barrier layer before growing a well layer. The step of growing the first barrier layer includes a first stage where a first nitride semiconductor layer containing In is grown with a first concentration of n-type impurity, a second stage where a second nitride semiconductor layer containing In is grown with a second concentration of n-type impurity higher than the first concentration, a third stage where a third nitride semiconductor layer containing In is grown with a third concentration of n-type impurity lower than the second concentration, and a fourth stage where a fourth nitride semiconductor layer is grown under a growth condition in which an amount of an impurity source gas is decreased or stopped.

Abstract: A method for producing micromechanical components is provided. A liquid starting material which can be cured by means of irradiation is applied onto a substrate. A partial volume of the starting material is cured by means of a local irradiation process using a first radiation source in order to produce at least one three-dimensional structure. The three-dimensional structure delimits at least one closed cavity in which at least one part of the liquid starting material is enclosed. Alternatively or in addition, a micromechanical component is provided that contains a liquid starting material, which is partly cured by means of irradiation, and at least one cavity in which the liquid starting material is enclosed.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.

Abstract: Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially, encapsulated in a dielectric material.

Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.

Abstract: Embodiments of the invention include a semiconductor structure comprising a light emitting layer. The semiconductor structure is attached to a support such that the semiconductor structure and the support are mechanically self-supporting. A wavelength converting material extends over the sides of the semiconductor structure and the support, wherein the wavelength converting material has a substantially uniform thickness over the top and sides of the semiconductor structure and the support.

Abstract: In a flexible organic light-emitting display device according to the present disclosure, an organic sealing film having a refractive index at least 0.3 smaller than a refractive index of each of first and second inorganic sealing films is disposed between the first and second inorganic sealing films, and, at the same time, a thickness of a front sealing layer is optimized to be less than 10 micrometers inclusive. Thus, the refractive index difference between the organic capping layer and the inorganic capping layer may be maximized to increase the micro-cavity effect. Further, by increasing the refractive index difference and optimizing the thickness in the front sealing layer, the micro-cavity effect may further be increased and, hence, the light extraction efficiency may be maximized.

Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

Abstract: An optical device wafer processing method for dividing an optical device wafer along a plurality of division lines to obtain a plurality of individual device chips includes applying a laser beam to a wafer substrate along each division line to thereby form a laser processed groove along each division line, and next forming a V groove along each laser processed groove on the optical device wafer by using a cutting blade having a V-shaped tip in the condition where each laser processed groove is removed by the cutting blade. A crack is formed so as to extend from the bottom of each laser processed groove due to a load applied from the cutting blade, thereby dividing the optical device wafer into the individual device chips. The depth of each laser processed groove is set smaller than the depth of cut by the cutting blade.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: An electroluminescent display device includes: a substrate including a subpixel; a thin film transistor disposed at the subpixel; an overcoat layer disposed on the thin film transistor; a first electrode disposed on the overcoat layer and electrically connected to the thin film transistor; a bank layer disposed on the overcoat layer and the first electrode, the bank layer including a plurality of openings configured to expose the first electrode and a plurality of opening patterns formed in a bar shape to expose the first electrode and connect the plurality of openings; an emitting layer disposed on the first electrode and the bank layer; and a second electrode disposed on the emitting layer.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.