Abstract: An apparatus for treating pixels or regions of a display panel includes a measuring device configured to measure a parameter of light emitted by one or more pixels of each region of the display panel. The apparatus includes a parameter comparator operably coupled to the measuring device and configured to select one or more pixels or one or more regions of the display panel such that the measured parameter of light emitted by the one or more pixels or the one or more regions exceeds a threshold value. The apparatus also includes a laser device configured to emit a laser beam onto the selected one or more pixels or the selected one or more regions.

Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.

Abstract: A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.

Abstract: An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.

Abstract: The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a first surface and a second surface wherein the second surface is opposed to the first surface. A mask layer is provided on the first surface of the substrate and a thin film layer is provided on the second surface of the substrate. The first surface of the substrate is diced through the mask layer to expose the thin film layer on the second surface of the substrate. A fluid from a fluid jet is applied to the thin film layer on the second surface of the substrate after the thin film layer has been exposed by the dicing step.

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: A method of forming a compound semiconductor substrate includes providing a crystalline base substrate having a first semiconductor material and a main surface, and forming a first semiconductor layer on the main surface and having a pair of tracks disposed on either side of active device regions. The first semiconductor layer is formed from a second semiconductor material having a different coefficient of thermal expansion than the first semiconductor material. The pair of tracks have a relatively weaker crystalline structure than the active device regions. The method further includes thermally cycling the base substrate and the first semiconductor layer such that the first semiconductor layer expands and contracts at a different rate than the base substrate. The pair of tracks physically decouple adjacent ones of the active device regions during the thermal cycling.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.

Abstract: A protective tape that improves solder bonding properties and reduces wafer warping. The protective tape includes, in the following order, an adhesive agent layer, a first thermoplastic resin layer, a second thermoplastic resin layer, and a matrix film layer. The protective tape satisfies the conditions expressed by the following formulae (1) to (3): Ga>Gb??(1) Ta<Tb??(2) (Ga*Ta+Gb*Tb)/(Ta+Tb)?1.4E+06 Pa.??(3) Ga represents a shear storage modulus of the first thermoplastic resin layer at a pasting temperature at which the protective tape is pasted; Gb represents a shear storage modulus of the second thermoplastic resin layer at the pasting temperature at which the protective tape is pasted; Ta represents a thickness of the first thermoplastic resin layer; and Tb represents a thickness of the second thermoplastic resin layer.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.

Abstract: A lead frame includes a metal plate, having a surface partitioned, by a concavity, into columnar areas, and a plating layer including stacked Ni, Pd and Au layers on the surface at top faces of the columnar areas, to form columnar pieces, which serve as internal connecting terminals, respectively, or as internal connecting terminals and pads, respectively. Each of the columnar pieces has, around a circumference of an upper portion thereof, curved regions intervening between straight regions. In each curved region, a side face of the plating layer protrudes outwardly in a horizontal direction from an uppermost portion of a side face of the metal plate in each of the columnar pieces. At a center of each straight region, the side face of the plating layer has substantially a same horizontal position as the uppermost portion of the side face of the metal plate in each of the columnar pieces.

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

Abstract: A method for processing a silicon substrate includes providing a combination of a first silicon substrate, a second silicon substrate, and an intermediate layer including a plurality of recessed portions, which is provided between the first silicon substrate and the second silicon substrate, forming a first through hole that goes through the first silicon substrate by executing etching of the first silicon substrate on a surface of the first silicon substrate opposite to a bonding surface with the intermediate layer by using a first mask, and exposing a portion of the intermediate layer corresponding to the plurality of recessed portions of the intermediate layer, forming a plurality of openings on the intermediate layer by removing a portion constituting a bottom of the plurality of recessed portions, and forming a second through hole that goes through the second silicon substrate by executing second etching of the second silicon substrate by using the intermediate layer on which the plurality of openings ar