Abstract: An organic light emitting device (OLED) comprises an anode; a cathode; and a light emitting layer, disposed between the anode and the cathode; wherein the light emitting layer comprises at least one luminescent compound; and wherein the transition dipole moment of the at least one luminescent compound is oriented parallel to the surface of the light emitting layer. A method of fabricating a light emitting layer, comprises the steps of providing a substrate; depositing less than 2 nm of a template material on the substrate; and depositing a composition comprising at least one light emitting compound on the template material.

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

Abstract: An electronic apparatus includes an organic light-emitting device including: a first electrode, a second electrode facing the first electrode, m light-emitting units stacked between the first electrode and the second electrode and including at least one emission layer; and m?1 charge generating layers, each located between two neighboring light-emitting units of the m light-emitting units and including an n-type charge generating layer and a p-type charge generation layer, wherein m is an integer of 2 or more, at least one of the m?1 p-type charge generation layers includes a first doping layer and a second doping layer, the first doping layer includes a first organic material and a first inorganic material, the second doping layer includes a second organic material and a second inorganic material, and the first inorganic material and the second inorganic material are different from each other.

Abstract: According to one aspect, a reconditioning wafer can include a carrier substrate that supports at least one array of regularly spaced protrusions configured to form indentations in a support surface of a wafer holding stage. The protrusions within the same array can have substantially the same shape and dimensions, thereby enabling a more reliable reconditioning process compared to prior art solutions. The protrusions may have the form of pyramids or pillars or other similar shapes with at least the tip of the protrusions formed of a material suitable to make the indentations. The reconditioning wafer can be obtainable by a molding technique wherein an array of molds can be created in a mold substrate. The molds can be filled with an indentation material such as diamond, and can be bonded to the carrier substrate. The mold substrate can be removed by thinning and wet etching.

Abstract: Provided are a phosphorescent organometallic complex and a use thereof. The metal complex has a ligand with a structure represented by Formula 1 and may be used as a light-emitting material in an electroluminescent device. These novel metal complexes can not only maintain low voltage and improve device efficiency in electroluminescent devices but also greatly reduce the half-peak width of light emitted by these devices so as to greatly improve color saturation of the light emitted by these devices, thereby providing better device performance. Further provided are an electroluminescent device and a compound formulation.

Abstract: A display apparatus includes a base substrate including a display region and a peripheral region that is a non-display region surrounding the display region, a plurality of data lines disposed in the display region on the base substrate and extending to the peripheral region, a bypass data line disposed in the display region and the peripheral region on the base substrate and electrically connected to at least one of the data lines, and a dummy pattern spaced apart from the bypass data line and disposed on a same layer as the bypass data line.

Abstract: A nanostructured cross-wire memory architecture is provided that can interface with conventional semiconductor technologies and be electrically accessed and read. The architecture links lower and upper sets of generally parallel nanowires oriented crosswise, with a memory element that has a characteristic conductance. Each nanowire end is attached to an electrode. Conductance of the linkages in the gap between the wires encodes the information. The nanowires may be highly-conductive, self-assembled, nucleic acid-based nanowires enhanced with dopants including metal ions, carbon, metal nanoparticles and intercalators. Conductance of the memory elements can be controlled by sequence, length, conformation, doping, and number of pathways between nanowires. A diode can also be connected in series with each of the memory elements. Linkers may also be redox or electroactive switching molecules or nanoparticles where the charge state changes the resistance of the memory element.

Abstract: A package device can include: a package body having a support body and an encapsulating body configured to encapsulate a conductive body of the package device; at least one extraction electrode electrically connected to the conductive body, and having a part exposed outside the package body; and where the support body is located on only part of a bottom surface of the encapsulating body, and protrudes from the bottom surface of the encapsulating body to form a cavity defined by the remaining exposed bottom surface of the encapsulating body and inner side surface of the supporting body.

Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Abstract: A semiconductor laser includes a substrate having a semiconductor layer sequence with an active layer that generates light during operation of the semiconductor laser, and a contact layer on a bottom side of the substrate opposite the semiconductor layer sequence, wherein the contact layer has at least one first partial region and at least one second partial region which are formed contiguously, the at least one first partial region is annealed, and the at least one second partial region is unannealed.

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

Abstract: An abatement system with liquid-ring pump maintains an exhaust line at a negative pressure during operation of a vacuum pump. The vacuum pump operates to exhaust process gas and by-products from a process chamber through a foreline. The vacuum pump exhausts the process gas to the abatement system with liquid-ring pump through the exhaust line. The overall life of the vacuum pump is increased significantly because the exhaust line is maintained at a negative pressure which reduces precipitation of gases in the vacuum pump thereby reducing by-product accumulation and damage to the vacuum pump. The liquid-ring pump receives the exhaust process gas from the vacuum pump and outputs gas to a burn chamber and liquid to a recirculation tank. Liquid is recycled through the liquid-ring pump thereby reducing accumulation of precipitated gas and by-product. The overall life of the liquid-ring pump and vacuum pump are increased.

Abstract: In one example, a semiconductor device comprises a substrate comprising a top side, a bottom side, and a conductive structure, a body over the top side of the substrate, an electronic component over the top side of the substrate and adjacent to the body, wherein the electronic component comprises an interface element on a top side of the electronic component, a lid over the interface element and a seal between the top side of the electronic component and the lid, and a buffer on the top side of the substrate between the electronic component and the body. Other examples and related methods are also disclosed herein.

Abstract: A quantum dot composition includes a quantum dot, and a ligand bonded to a surface of the quantum dot, wherein the ligand includes a head portion bonded to the surface of the quantum dot, a connecting portion connected to the head portion and including a metal, and a tail portion coordinated to the metal of the connecting portion. The quantum dot composition according to the present embodiments is used to form an emission layer of a light emitting element, and may thus increase service life and luminous efficiency of the light emitting element including the emission layer formed using the quantum dot composition.

Abstract: To reduce the dark current ratio. A photoelectric conversion element 10 including an anode 16, a cathode 12, an active layer 14 provided between the anode and the cathode, and at least one electron transportation layer 13 provided between the active layer and the cathode, in which the electron transportation layer contains an insulating material and a semiconductor material; a difference between a work function of the electron transportation layer and a work function of the cathode is 0.88 eV or more; the active layer contains a p-type semiconductor material and an n-type semiconductor material; and a work function of the electron transportation layer (Wf1) and an energy level of a lowest occupied molecular orbital of the n-type semiconductor material (LUMO) satisfy the following Formula (2): |LUMO|?Wf1?0.06 eV??(2).

Abstract: Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.

Abstract: The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.

Abstract: An imaging apparatus includes a pixel array unit including a plurality of pixel groups, each of the plurality of pixel groups being one of i) a normal pixel group including only normal pixels, or ii) a mixed pixel group including at least one normal pixel and at least one phase difference detection pixel, wherein the pixel array unit comprises at least one normal pixel group and at least one mixed pixel group. For each normal pixel group, the normal pixels receive light transmitted through a same colored color filter. For each mixed pixel group, the at least one phase difference detection pixel shares an on-chip lens with at least one other phase difference detection pixel and receives light transmitted through a same colored color filter as the at least one other phase difference detection pixel.

Abstract: A display panel is provided. At least two first wires in a second direction are electrically connected to each other and at least two second wires in the second direction are electrically connected to each other. The space in the second direction is fully used to arrange the first wires and the second wires to ensure the number of first via holes disposed corresponding to the first wires and the number of second via holes disposed corresponding to the second wire, thereby ensuring the connectivity of a transparent conductive block that bridges the first wires and the second wires through the first via holes and the second via holes.