Abstract: Provided are a substrate storage apparatus and a substrate processing apparatus using the substrate storage apparatus. The substrate storage apparatus includes a housing having a loading/unloading port for loading/unloading of a substrate and configured to provide a loading space for a loaded substrate, a separation membrane coupled to the housing to divide the loading space into a plurality of separation spaces isolated from each other, a gas supplier configured to supply a purge gas into the loading space to clean the substrate, a gas discharger configured to discharge the purge gas accommodated in the loading space, and a controller configured to control supply and discharge of the purge gas for each of the plurality of separation spaces.

Abstract: A substrate aligning method includes receiving a substrate by moving a substrate support from an outside of an outer periphery toward a central portion of the substrate along the substrate; and aligning the substrate such that the substrate support moves from a position different from a position partially upwardly warped along an outer peripheral edge of the substrate and a position partially downwardly warped along the outer peripheral edge of the substrate toward the central portion of the substrate so as to receive the substrate.

Abstract: Inorganic-organic hybrid structures having both ionic and coordinate bonds in a molecular cluster possessing the features of structural diversity, high luminescence and stability, and excellent dispersibility, suitable for use as lighting phosphors.

Abstract: The present disclosure describes a system and a method for an ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.

Abstract: An organic electroluminescence device of an embodiment includes a first electrode, a second electrode, and an emission layer between the first electrode and the second electrode, wherein the emission layer includes a polycyclic compound represented by Formula 1 and shows high emission efficiency and excellent color reproducibility.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.

Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: A piezoelectric micromachined ultrasonic transducer (PMUT) device includes a layer of piezoelectric material that is activated and sensed by an electrode and a conductive plane layer. The conductive plane layer may be electrically connected to processing circuitry by a via that extends through the piezoelectric layer. One or more isolation trenches extend through the conductive plane layer to isolate the conductive plane layer from other conductive plane layers of adjacent PMUT devices of a PMUT array.

Abstract: The present disclosure relates to the field of display technologies, and discloses a display panel, a preparing method thereof, and a display device. The display panel has a bending area, and the display panel includes a sensing component; the sensing component includes a differential bridge connection circuit composed of a first strain sensor, a second strain sensor, a third strain sensor, and a fourth strain sensor; the first strain sensor, the second strain sensor, the third strain sensor, and the fourth strain sensor are resistance transducers, and are located in the bending area; the first strain sensor and the fourth strain sensor constitute first opposite bridge arms; the second strain sensor and the third strain sensor constitute second opposite bridge arms, and the first opposite bridge arms and the second opposite bridge arms are separately located on two sides of a neutral layer of the display panel.

Abstract: A method for fabricating a bridge structure in a quantum mechanical device includes providing a substructure including a substrate having deposited thereon a layer of a first superconducting material divided into a first portion, a second portion and a third portion that are electrically insulated from each other; depositing a sacrificial layer on the substructure; electrically connecting the first portion and the second portion with a strip of a second superconducting material, the second superconducting material being different from the first superconducting material; and removing a portion of the sacrificial layer so as to form a bridge structure over the third portion between the first portion and the second portion, the bridge structure electrically connecting the first portion to the second portion while not electrically connecting the third portion to the first portion and not electrically connecting the third portion to the second portion.

Abstract: A display device includes a flexible substrate including a first surface and a second surface facing the first surface; a TFT array layer provided on the first surface; a display element layer provided on the TFT array layer; a first heat releasing layer provided on the second surface; a first protective layer provided on the same side as the second surface; a second heat releasing layer provided on the display element layer; and a second protective layer provided on the display element layer. The second heat releasing layer has a light transmittance of 90% or higher.

Abstract: An array of piezoelectric micromachined ultrasound transducers (PMUTs) has a layer of piezoelectric material that requires poling during fabrication in order to properly align the piezoelectric dipoles to create a desired ultrasonic signal. The PMUT may have an interconnected set of lower electrodes that are fabricated between a processing layer of the PMUT and the piezoelectric layer. An upper electrode is fabricated overlaying the piezoelectric layer, and a poling voltage is applied between the upper electrode and the interconnected set of lower electrodes. After poling is complete, portions of the interconnected set of lower electrodes are removed to permanently isolate permanent lower electrodes from each other.

Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.

Abstract: Process for producing semiconductor devices in a substrate, comprising: photolithography of a pattern of a reticle onto a portion of the substrate, defining first elements of the semiconductor devices, an exposure of the pattern being repeated a plurality of times in order to define all of the devices, photolithography of a pattern of an etch mask over all of the substrate, etching photolithography patterns into one portion of the thickness of the substrate, wherein first dicing lanes encircling the devices are included in the pattern of the etch mask and/or of the reticle, and the photolithography of the etch mask defines second dicing lanes defined by predetermined fracture lines of the edges of the substrate, and furthermore comprising the implementation of a step of irradiating the substrate with a laser beam through the first and second dicing lanes.

Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

Abstract: The present disclosure provides a flexible display module and a display device. The flexible display module includes a flexible display panel and a driving chip, and the flexible display panel includes a flexible substrate, a driving circuit layer, and a light-emitting functional layer which are sequentially disposed. The driving circuit layer includes a piezoelectric layer. The piezoelectric layer can convert stress generated when the display panel is bent into an electrical signal, which is transmitted to the driving chip through the driving circuit and controls each area of the flexible display panel to emit light of a predetermined intensity.

Abstract: The present technology relates to a solid-state imaging element and electronic equipment that allow an increase in the signal charge amount Qs that each pixel can accumulate. A solid-state imaging element according to the first aspect of the present technology includes: a photoelectric conversion section formed in each pixel; and an inter-pixel separation section separating the photoelectric conversion section of each pixel, in which the inter-pixel separation section includes a protruding section having a shape protruding toward the photoelectric conversion section. The present technology can be applied to a back-illuminated CMOS image sensor, for example.

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.