Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

Abstract: In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to an internal die mounting pad of either a leadframe or an alternative type of substrate. Appropriate interconnect methods between the lid, the die pad, and the ground connections exterior to the semiconductor package include, but are not restricted to, conductive adhesives, wire bonding, bumps, tabs, or similar techniques.

Abstract: A semiconductor device in an embodiment includes a first region of a second conductivity type between a first electrode and a second electrode and a second region of a first conductivity type between the first region and the second electrode. a third region of the second conductivity type is between the second region and the second electrode. A fourth and fifth region of the first conductivity type are between the third semiconductor region and the second electrode. The fourth and fifth regions are adjacent to each other. A dopant concentration in the fifth region is less than a dopant concentration in the fourth region. A third electrode contacts the second region, the third region, the fourth region, and the fifth region via an insulating film.

Abstract: The present invention relates to a phase-change memory device structure and the materials used. The structure comprises a substrate, a single or multiple sandwich-memory-unit(s), a first electrode, and a second electrode. The sandwich-memory-unit contains an upper barrier layer, a lower barrier layer, and a memory layer therebetween. The thickness of the memory-layer is less than 30 nm. The present invention provides a phase-change memory device with a high Tc and a low volume changing rate during phase-change.

Abstract: The invention relates to a method for producing a component comprising a conductive grid insulated from a semiconductor monocrystalline diamond substrate by an insulating region, comprising the following steps: a) oxygenating the surface of the substrate so as to replace the hydrogen surface terminations of the substrate with oxygen surface terminations; and b) forming the insulating region on the surface of the substrate by repeated monatomic layer deposition.

Abstract: A device having a first active transistor, a second active transistor, an isolation gate structure, and an active region underlying each of the first active transistor, the second active transistor, and the isolation gate structure is provided. The first and second active transistors each have a metal gate with a first type of conductivity (e.g., one of n-type and p-type). The isolation gate structure interposes the first and second active transistors. The isolation gate structure has a metal gate with a second type of conductivity (e.g., the other one of n-type and p-type). A method of fabricating devices such as this are also described.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.

Abstract: Certain embodiments provide a semiconductor device including a semiconductor substrate, a side wall portion, a cap substrate, a plurality of external connection terminals, and a ground conductor. The semiconductor substrate includes a semiconductor element on its front surface. The side wall portion has conductivity and is provided on the front surface of the semiconductor substrate so as to surround the semiconductor element. The cap substrate is provided on the side wall portion so as to be electrically connected to the side wall portion. Each of the plurality of external connection terminals is provided on a back surface of the semiconductor substrate so as to be electrically connected to the semiconductor element. The ground conductor is provided to be electrically connected to the side wall portion on the entire back surface of the semiconductor substrate except an area in which the plurality of external connection terminals is provided.

Abstract: Provided are graphene transistors having a tunable barrier. The graphene transistor includes a semiconductor substrate, an insulating thin film disposed on the semiconductor substrate, a graphene layer on the insulating thin film, a first electrode connected to an end of the graphene layer, a second electrode that is separate from an other end of the graphene layer and contacts the semiconductor substrate, a gate insulating layer covering the graphene layer, and a gate electrode on the gate insulating layer, wherein an energy barrier is formed between the semiconductor substrate and the graphene layer.

Abstract: A semiconductor substrate includes a sapphire substrate including a c-plane main surface and a groove in a surface thereof, the groove including side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. The side surfaces of the groove are an a-plane of sapphire. An axis of the Group III nitride semiconductor layer, perpendicular to one of the side surface of the groove, is a c-axis of Group III nitride semiconductor. A plane of the Group III nitride semiconductor, parallel to the main surface of the sapphire substrate, is an a-plane of Group III nitride semiconductor.

Abstract: A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

Abstract: An organic semiconductor device includes an organic semiconductor, an electrode electrically connected to the organic semiconductor, and a self-assembled monolayer positioned between the organic semiconductor and the electrode, the self-assembled monolayer including a monomer having an anchor group at one end and an ionic functional group at another end.

Abstract: A semiconductor high-side driver including; an input terminal; an output terminal to be coupled to a load element; an output MOS transistor having a drain coupled to a power supply terminal, a source coupled to the output terminal and a gate; a sense MOS transistor having a drain coupled to the power supply terminal, a gate coupled to the gate of the output MOS transistor and a source; a control circuit coupled to the input terminal and provides a control signal to the gate of the output MOS transistor; and a voltage detection circuit which includes: a threshold voltage generation circuit having a first terminal coupled to the power supply terminal and a second terminal which generates a voltage lower than a voltage of the power supply terminal by a threshold voltage; and a comparator.

Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.

Abstract: An object of the present invention is to achieve improvement in performance of a thin film transistor including an oxide as a gate insulating layer, or simplification and energy saving in the processes of producing such a thin film transistor. A thin film transistor (100) of the present invention includes a first oxide layer (possibly containing inevitable impurities) (32) consisting of lanthanum (La) and tantalum (Ta), which has a surface (32a) formed after a precursor layer obtained from a precursor solution as a start material including a precursor containing lanthanum (La) and a precursor containing tantalum (Ta) as solutes is exposed to a hydrochloric acid vapor, between a gate electrode (20) and a channel (52). Moreover, in the thin film transistor, the surface (32a) of the first oxide layer (32) is in contact with the channel (52).

Abstract: ESD protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base well region having a first conductivity type, a collector region of the opposite conductivity type, and a second base well region having a dopant concentration greater than the first base well region, and a portion of the second base well region is disposed between the first base well region and the collector region. A third base well region with a different dopant concentration is disposed between the collector region and the second base well region. At least a portion of the first base well region is disposed between a base contact region and an emitter region within the second base well region.

Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.

Abstract: A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.