Abstract: Disclosed is a light emitting device including a support substrate, a transistor unit disposed at one side of the upper surface of the support substrate, a light emitting device unit disposed at the other side of the upper surface of the support substrate, and an insulating layer disposed between the transistor unit and the light emitting device unit and between the support substrate and the transistor unit and isolating the transistor unit from the light emitting device unit.

Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: An electrical interconnect has a non-planar ceramic substrate with opposing first and second ends. A first conductive layer having first and second opposing sides is disposed within the ceramic substrate with one of the first and second opposing sides exposed at the first end and one of the first and second opposing sides exposed at the second end. The electrical interconnect is useful to join an integrated circuit in a hybrid package to a circuit board in high frequency communication applications.

Abstract: A method of manufacturing a semiconductor element is provided. The method includes the following steps. A carrier and a mold are provided. A first patterned conductive layer including a plurality of traces is formed on the carrier. A second patterned conductive layer is formed on the first patterned conductive layer. The carrier is disposed with the mold to form at least one mold cavity. The mold cavity is infused with a molding material. The molding material fills the mold cavity to encapsulate the first and second patterned conductive layers. The carrier is removed by etching to expose the plurality of traces embedded in the molding material without affecting the width of the traces.

Abstract: A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed.

Abstract: A light emitter is disclosed herein. The light emitter may have a lead frame and a plastic reflector cup. The lead frame may have a planar portion; a bond area having a light-emitting diode attached thereto; and at least two terminals configured for surface mount technology. The reflector cup may be proximate the bond area and may have an opening, wherein light emitted from the light-emitting diode passes through the opening; a side wall extending between the planar portion and the opening; and a clear lens located proximate the opening and attached to the reflector cup. The combination of the lens and the reflector cup causes a light beam originating from the light-emitting diode to be less than fifteen degrees.

Abstract: Getter structure comprising a substrate and at least one getter material-based layer mechanically connected to the substrate by means of at least one support, in which the surface of the support in contact with the substrate is smaller than the surface of a first face of the getter material layer, in which said first face is in contact with the support, and a second face of the getter material layer, opposite said first face is at least partially exposed.

Abstract: Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling, and is further diced at the fixed clock-cycle distance, and flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.

Abstract: The invention is directed to an avalanche photodiode containing a substrate and semiconductor layers with various electro-physical properties having common interfaces both between themselves and with the substrate. The avalanche photodiode may be characterized by the presence in the device of at least one matrix consisting of separate solid-state areas with enhanced conductivity surrounded by semiconductor material with the same type of conductivity. The solid-state areas are located between two additional semiconductor layers, which have higher conductivity in comparison to the semiconductor layers with which they have common interfaces. The solid-state areas are generally made of the same material as the semiconductor layers surrounding them but with conductivity type that is opposite with respect to them. The solid-state areas may be made of a semiconductor with a narrow forbidden zone with respect to the semiconductor layers with which they have common interfaces.

Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.

Abstract: A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.

Abstract: An electronic chip is provided, including an electronic circuit located at a front face of a substrate; a capacitive element placed at a back face of the substrate and facing the electronic circuit, and electrically connected to the electronic circuit by a first electrical connection and a second electrical connection, the first electrical connection including at least a first electrically conducting via passing through the substrate, the electronic circuit being configured to measure a value of electrical capacitance of the capacitive element between the first and the second electrical connections; and a plurality of second vias or trenches passing through the back face of the substrate and a part of the thickness of the substrate, and extending toward the electronic circuit such that bottom walls of the plurality of second vias or trenches are separated from the electronic circuit by at least one non-zero distance.

Abstract: According to the present invention, a method for manufacturing a compound semiconductor comprises: forming a graphene-derived material layer on either a first selected substrate or a first selected compound semiconductor layer; forming a second compound semiconductor layer of at least one layer on at least said graphene-derived material layer, and changing the graphene-derived material layer so as to separate said second compound semiconductor layer of at least one layer.

Abstract: A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.

Abstract: The method includes forming a metal interconnection layer and a first interlayer insulating layer on a semiconductor substrate, forming a reservoir capacitor region by etching the first interlayer insulating layer to expose the metal interconnection layer, forming a barrier metal layer on the reservoir capacitor region, forming a sacrificial insulating layer on the barrier metal layer in a lower portion of the reservoir capacitor region, performing a pre-cleaning process to remove the barrier metal layer on a sidewall of the reservoir capacitor region, and removing the sacrificial insulating layer.

Abstract: A semiconductor substrate includes a sapphire substrate including an a-plane main surface and a groove in a surface thereof, the groove includes side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. Both side surfaces of the groove assume a c-plane of sapphire. An axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor. A plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.

Abstract: A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.