Abstract: Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different embodiments for the resilient contact probes is also disclosed. The carriers of the present invention may be secured to an interface board (i.e., a printed circuit board (PCB)) and assembled with a substrate (e.g., a wafer having integrated circuitry thereon, a PCB, etc.). The resilient contact probes electrically contact the terminal pads of the interface board and the electrical contacts of the substrate to enable electrical testing of the substrate. The configuration of the resilient contact probes, in combination with the carrier body, enables preferential, high mechanical loading of the terminal pads with controlled, predictable loading of the electrical contacts. Methods of making and use are also disclosed, as are a plurality of embodiments of resilient contact probes.

Abstract: The present invention is an attachment device and a method for fastening and removing an electrical cable monitoring instrument to an electrical cable. The attachment device comprises monitoring instrument sensor with opening for positioning electrical cable such that said electrical cable can be positioned to pass through the sensitive volume at least partially surrounded by said sensor, at least one elongated elastic member securely attached to said cable monitoring instrument such that, when elastically deformed to a shape characterized by high mechanical energy such that deformed elastic member allows said electrical cable access to and from the sensitive volume at least partially surrounded by said monitoring instruments sensor.

Abstract: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

Abstract: Optoelectronic properties of optical communication LEDs, LDs and PDs should be examined in a wide range of temperatures between ?40° C. and +85° C. Low temperature photocharacteristics of as-chip devices are tested by preparing an inspection stage cooled at a low temperature encapsulated in a shield casing with a front opening, conveying a chip of LD, LED or PD by a collet via the opening, placing the chip on the cold stage, blowing the stage and chip with cool dry air for preventing the chip from wetting, touching the chip by a probe, applying a current/voltage to the chip, examining emission/detection of the chip and taking the chip off via the opening by the collet.

Abstract: A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated.

Abstract: A probe for electrical test comprises a probe body having a base end attached to a support base plate through a solder and a front end continuous with said base end and a surface layer showing a conductivity higher than that of the probe body and a solder wettability higher than that of the probe body and extending on the surface of the probe body from the base end to the front end. In the vicinity of the base end of the surface layer, a shield region having a smaller solder wettability than that of the surface layer is formed across the surface layer.

Abstract: The measurement unit measures a voltage by converting it from analog to digital and outputs a measurement value. The changeover unit, being connected to a battery and a reference voltage source generating a highly accurate fixed voltage, selects one of them and applies it to the measurement unit. The voltage value output unit makes the changeover unit select a fixed voltage generated by a predetermined voltage source, makes the measurement unit measure it as a reference voltage and generates calculation-use information for calculating a voltage value from a measurement result based on a measurement value of the fixed voltage and a voltage value of the reference voltage. The voltage value output unit, when making the changeover unit select a voltage of the battery and making the measurement unit measure it, uses the measurement value of it and the calculation-use information to calculate and output a voltage value of the battery.

Abstract: A test device for testing a device under test, wherein the test device is adapted for providing a connection to a central controller, the test device comprising a first interface for receiving a test procedure activation signal from the central controller, and a processor for performing a test procedure on the basis of a test procedure data upon receipt of the test procedure activation signal, wherein the processor is capable of adjusting the test procedure upon receipt of a feedback signal from the device under test.

Abstract: A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least one resident memory socket fixed to the motherboard. A remote memory socket is provided and located a distance from the resident memory socket, such as on a periphery of the motherboard. The remote memory socket is coupled to the resident memory socket by a conductor assembly such as a ribbon cable and an adapter. A memory module is placed in the remote memory socket and tested using a signal or combination of signals from the processor. A plurality of motherboards, each being configured with remote memory sockets, may be combined to form a testing system suitable for use with an automated handler.

Abstract: A testing device for performing a white balance test on a display device of an electronic equipment is disclosed. The testing device includes a supporting body, a testing member, a position-adjusting member and a clipping member. The testing member is disposed on the supporting body and used to mask the display device and perform the white balance test on the display device. The testing member has a testing opening. The position-adjusting member is disposed on the supporting body for adjusting a position where the testing member is disposed on the supporting body. The clipping member presses the display device against the testing member when the position-adjusting member makes the testing member aligned with the display device such that the display device can be closely contacted with the testing member. Thus, the white balance test can be performed on the display device through the testing member.

Abstract: The semiconductor device (11) of the invention comprises a circuit covered by a passivation structure (50). It is provided with a first and a second security element (12A, 12B) which comprise local areas of the passivation structure (50), and with a first and a second electrode (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which impedances differ. This is realized in that the passivation structure has an effective dielectric constant that varies laterally over the circuit. Actual values of the impedances are measured by measuring means and transferred to an access device by transferring means. The access device comprises or has access to a central database device for storing the impedances. The access device furthermore may compare the actual values with the stored values of the impedances in order to check the authenticity or the identity of the semiconductor device.

Abstract: An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures.

Abstract: A chuck for a probe station.

Abstract: A chuck for a probe station.

Abstract: A interface board is provided with a first and second contact instruments each comprising a first and second contact terminal groups to which a first to third type semiconductor devices having different numbers of external terminals used can be connected. The first contact terminal group of the first contact instrument is connected to the corresponding terminals of the second contact terminal group of the second contact instrument using bridging lines. One end of each bridging wire is connected to a driver output pin of an channel provided in pin electronics. The other end of the bridging wire is connected to a comparator input pin of the IO channel provided in the pin electronics. The first contact terminal group of the second contact instrument is connected, using different connection lines, to a driver output pin and a comparator input pin of an IO channel provided in the pin electronics.

Abstract: In one embodiment, the invention provides a test assembly for electrically connecting a test component to a testing machine for testing electrical circuits on the test component. The assembly comprises a contactor assembly to interconnect with the test component, a probe assembly to mechanically support the contactor assembly and electrically connect the contactor assembly to the testing machine, and a clamping mechanism comprising a first clamping member and a second clamping member, the clamping members being urged together to exert a clamping force to deform contactor bumps of an electrical connection between the probe assembly and the contactor assembly.

Abstract: A system and method for sensing the proximity of an electronic device, in particular, a radio frequency mobile communication device such as a mobile telephone, wireless modem equipped portable computer, or the like to a body employs an antenna capable of altering its impedance for changing the amount of radio frequency electromagnetic energy reflected by the antenna when the antenna is in proximity to the body. The radio frequency electromagnetic energy reflected by the antenna is measured and used for determining proximity of the antenna to the body.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: An integrated circuit for use at a reduced Vdd voltage. An integrated circuit is designed and implemented such that it is usable at a voltage less than an industry standard Vdd voltage. The integrated circuit may include a voltage filter that may either be implemented on the integrated circuit or external to the integrated circuit. The voltage filter receives an industry standard IC voltage and produces a filtered voltage that is that some value below the industry standard IC voltage. The voltage filter also removes noise from the industry standard IC voltage. The integrated circuit includes signal processing circuitry that is designed and implemented to improve signal quality and to operate at the filtered voltage.