Patents Examined by Ernest F. Karlsen
  • Patent number: 7432698
    Abstract: A modular active test probe and removable tip module therefor. Within the scope of the invention, there is a probe tip module comprising a first probe tip adapted for probing a circuit under test to receive a signal therefrom. The probe tip module includes an amplifier having a first input solidly connected to the probe tip, an output connected to an output connector, and a housing for supporting the probe tip, the amplifier, and the output connector. A probe body is cooperatively adapted with the housing for repeatably removably receiving at least the output connector.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: October 7, 2008
    Assignee: LeCroy Corporation
    Inventors: Julie A. Campbell, Lawrence W. Jacobs, Stephen Mark Sekel
  • Patent number: 7423442
    Abstract: According to one embodiment of the invention, a method for early qualification of semiconductor device includes performing initial testing on a semiconductor device, receiving fail data on the semiconductor device, determining a solution model for the semiconductor device based on the fail data, storing the solution model, performing subsequent testing on the semiconductor device, and comparing a result of the subsequent testing to the solution model.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: September 9, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: John W. Steck, Jr.
  • Patent number: 7423419
    Abstract: A chuck for a probe station.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: September 9, 2008
    Assignee: Cascade Microtech, Inc.
    Inventor: John Dunklee
  • Patent number: 7420384
    Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: September 2, 2008
    Assignee: Xilinx, Inc.
    Inventors: Sabih Sabih, Jari Vahe
  • Patent number: 7420381
    Abstract: A test configuration for double sided probing of a device under test includes a holder to secure the device under test in a first orientation, a calibration substrate secured in a second orientation and a probe capable of calibration using the calibration substrate and probing the device under test.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: September 2, 2008
    Assignee: Cascade Microtech, Inc.
    Inventors: Terry Burcham, Peter McCann, Rod Jones
  • Patent number: 7417448
    Abstract: A system may include biasing of diodes of a temperature sensor disposed in an integrated circuit die using a current from an off-die current source, generation of a voltage based on the current and a temperature of the integrated circuit die, and determination of a first temperature based on the voltage. Such a system may further include amplification of the voltage using an oscillator and a chopper stabilizer, determination of a first amplified voltage associated with a first state of the oscillator and a second amplified voltage associated with a second state of the oscillator, and determination of a third voltage based on the first amplified voltage and the second amplified voltage, wherein determination of the first temperature based on the voltage comprises determination of the first temperature based on the third voltage.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: Chee H. Lim, Jed D. Griffin, Kifah M. Muraweh
  • Patent number: 7417444
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
  • Patent number: 7417419
    Abstract: A current coil arrangement in an electricity meter includes first and second current coils. The first current coil has two current blades and a middle portion extending therebetween. The two current blades are configured to be received by a utility meter socket device. The middle portion and the current blades are integrally formed of a conductive material. The first current coil is asymmetrical about the midpoint between the two current blades, and is disposed at least partially within the electricity meter. The second current coil is disposed at least partially within the electricity meter. The second current coil constructed substantially identical to the first current coil.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: August 26, 2008
    Assignee: Landis+Gyr, Inc.
    Inventor: Ronald C. Tate
  • Patent number: 7414417
    Abstract: According to one aspect of the invention, a contact sheet for testing electronic parts, comprising an insulating porous layer; and a connection electrode which is disposed on the insulating porous layer and electrically connect the electrode or terminal of the electronic parts and the terminal of a test apparatus; wherein the connection electrode is embedded below at least one main surface of the insulating porous layer.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake
  • Patent number: 7414390
    Abstract: A signal detection contactor has a contactor main body and a plurality of coaxial bodies. Each coaxial body includes a core wire. The core wire is used for coming into contact with a probe of a prober and for receiving a signal transmitted from a tester, in order to calibrate a phase difference among signals transmitted through a plurality of probes.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 19, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Chihiro Watanabe
  • Patent number: 7397259
    Abstract: A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kanak B. Agarwal, Jerry D. Hayes, Ying Liu
  • Patent number: 7397260
    Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill, Tom C. Lee, Baozhen Li, Paul S. McLaughlin, Du B. Nguyen, Hazara S. Rathore, Timothy D. Sullivan, Chih-Chao Yang
  • Patent number: 7391227
    Abstract: Disclosed herein are a sheet-like probe capable of surly preventing positional deviation between electrode structures and electrodes to be inspected by temperature changes in a bum-in test, even when the object of inspection is a wafer having a large area of 8 inches or greater in diameter or a circuit device, the pitch of electrodes to be inspected of which is extremely small, and thus capable of stably retaining a good electrically connected state, and a production process and applications thereof. The sheet-like probe of the present invention comprises a contact film obtained by holding a plurality of electrode structures arranged in accordance with a pattern corresponding to respective electrodes to be connected and having a front-surface electrode part exposed to a front surface and a back-surface electrode part exposed to aback surface by an insulating film composed of a flexible resin, and a frame plate supporting the contract film.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: June 24, 2008
    Assignee: JSR Corporation
    Inventors: Kazuo Inoue, Katsumi Sato
  • Patent number: 7385386
    Abstract: A probe card transporting apparatus includes a truck and transporting mechanism. The truck can move on a floor surface freely. The transporting mechanism is arranged above the truck to be able to separate from and come into contact with it. The transporting mechanism transports a probe card between the truck and a prober. The transporting mechanism has a base and arm mechanism. The arm mechanism moves forward/backward on the base. An aligning mechanism and fixing mechanism are provided on the base. The aligning mechanism serves for alignment with the prober. The fixing mechanism serves for fixing to the prober.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: June 10, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Amemiya, Koji Kawaguchi, Masaru Suzuki
  • Patent number: 7355435
    Abstract: On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Ferraiolo, Anuja Sehgal, Peilin Song, Michael A. Sperling
  • Patent number: 6967494
    Abstract: A wafer-interposer assembly (10) includes a semiconductor wafer (12) having a plurality of semiconductor die (14) that have a plurality of first electrical contact pads (16). An interposer (22) is connected to the semiconductor wafer (12) such that a plurality of second electrical contact pads (26) associated with the interposer (22) are respectively connected to at least some of the first electrical contact pads (16) via conductive attachment elements (20). A communication interface (28) is integrally associated with the interposer (22) and electrically connected to at least some of the plurality of second electrical contact pads (26). The interposer (22) and the semiconductor wafer (12) are operable to be singulated into a plurality of chip assemblies.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: November 22, 2005
    Assignee: Eaglestone Partners I, LLC
    Inventor: Jerry D. Kline
  • Patent number: 6784677
    Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 31, 2004
    Assignee: FormFactor, Inc.
    Inventors: Charles A. Miller, John Matthew Long
  • Patent number: 6744268
    Abstract: A specimen probing apparatus in provided including a vacuum chamber within which a carrier for the specimen to be probed and a probe assembly are positioned. The housing for the chamber is preferably constructed to allow a variety of options for electrically isolating the test environment in the chamber. Also, unique drive or shift assemblies for the carrier and probe assembly are disclosed for allowing precision movements thereof in the vacuum chamber.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: June 1, 2004
    Assignee: The Micromanipulator Company, Inc.
    Inventor: Kenneth F. Hollman
  • Patent number: 6741070
    Abstract: A wide-band RF signal power detecting element includes, on an insulating substrate (21), at least one thin-film resistor (22a) for absorbing the power of a signal to be measured and generating heat, first and second ground electrodes (27, 28) formed by thin-film conductors, a first thin-film connecting portion (24) for electrically connecting the first ground electrode (27) to the thin-film resistor (22a), a second thin-film connecting portion (25) for electrically connecting the second ground electrode (28) to the thin-film resistor (22a) and narrowing the gap between the first and second thin-film connecting portions (24, 25) toward the thin-film resistor (22a), and an input electrode (26) formed between the first and second ground electrodes (27, 28) and electrically connected to the thin-film resistor (22a).
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 25, 2004
    Assignee: Anritsu Corporation
    Inventor: Setsuo Kodato
  • Patent number: 6717426
    Abstract: A blade-like connecting needle for measuring a semiconductor wafer has an increased capability for measuring a small current and also has stable characteristics. The blade-like connecting needle includes a blade signal line for transmitting signal from the semiconductor wafer, a support insulator covering at least a portion of the blade signal line, a plurality of blade guard patterns disposed in or on the support insulator for electromagnetically shielding the blade signal line, and a probe supported on the support insulator and connected to the blade signal line. There are also disclosed processes of producing the blade-like connecting needle. A method for manufacturing a coaxial or hollow blade-like connecting needle is also provided.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: April 6, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Yukoh Iwasaki