Abstract: A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The spray heads and probe head are disposed in a sealed manner inside a spray chamber that, during operation, is urged in a sealing manner onto a sealing plate holding the integrated circuit under test. The atomized mist cools the integrated circuit and then condenses on the spray chamber wall. The condensed fluid is pumped out of the chamber and is circulated in a chiller, so as to be re-circulated and injected again into the micro-spray heads. The pressure inside the spray chamber may be controlled to provide a desired boiling point.

Abstract: A device for interfacing a test head and a prober is disclosed using wires or cables to provide the connection from a probe card interface boards to the probe card. The use of wires or cables, in place of the traditional pogo pin arrangement allows for more reliable and efficient testing, as well as additional high performance tests to be run. Optionally, a probe interface contains a stiffening member with multiple sidewalks and individual, configuration-specific probe card interface strips are connected to a probe card through zero insertion force clamps. The probe card interface attaches to the test head using standard probe interface board (“PIB”) docking mechanics. The assembly is then connected to a probe to carry out the testing procedures.

Abstract: A chuck for a probe station.

Abstract: The burn-in apparatus includes a water supply system and a sprayer and has a structure such that water is converted into mist and sprayed onto the upper surface of a device attached to a socket of a burn-in board. The amount of heat generated by the device that generates high heat is removed by the amount of heat that includes a large latent heat from when the mist falls on the upper surface and is evaporated. Burn-in of the device is conducted while it is being cooled to the target temperature.

Abstract: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.

Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: The present invention discloses a universal grid composite circuit board testing tool having a probe station, a clamp base and a conducting wire base. The probe station and clamp base separately have a plurality of conducting probes and long needles. Both ends of the long needle are electrically contacted with the testing point and conducting probe of the testing printed circuit board. The conducting wire base includes a conducting wire contact point electrically connected to a plurality of conducting probes in the probe station at the same time, such that when a testing printed circuit board is tested, it is not necessary to prepare a new probe station and a new conducting wire base. The test simply requires users to change the installation positions of the long needles and run a comparison program according to the positions of the testing points of the testing printed circuit board.

Abstract: Structure and methods of determining the complete location of a buried short using voltage contrast inspection are disclosed. In one embodiment, a method includes providing a test structure having a PN junction thereunder; and using the PN junction to determine the location of the buried short using voltage contrast (VC) inspection. A test structure may include a plurality of test elements each having a PN junction thereunder, wherein a location of the buried short within the test structure can be determined using the PN junction and the VC inspection. The PN junction forces a change in illumination brightness of a test element including the buried short, thus allowing determination of the complete location of a buried short.

Abstract: The invention relates to methods for positioning of a substrate and contacting of the test object for testing with a test apparatus with an optical axis and corresponding devices. Thereby, the substrate is put on the holder. The substrate is positioned relative to the optical axis. A contact unit is also positioned relative to the optical axis, whereby the contact unit is positioned independent of the positioning activity of the substrate. Thereby, a flexible contacting of test objects on the substrate can be realized.

Abstract: An electric current measurement device includes a housing defining first and second open ends sealed by first and second sealing means, respectively; a first optical fibre received in an aperture in the first sealing means and in optical communication with a first optical lens in the housing; a first polarisation filter in the housing in optical communication with the first lens; a magneto-optical rod within the housing in optical communication with the first polarisation filter; a second polarisation filter in the housing in optical communication with the rod; and a second optical lens in the housing in optical communication with the second polarisation filter. The second sealing means has an aperture for receiving a second optical fibre fixed to the second lens. First and second lids, attachable to the first and second housing ends, respectively, include apertures for receiving the first and second optical fibres, respectively.

Abstract: A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit to transition between normal operation and the test mode.

Abstract: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.

Abstract: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.

Abstract: The invention provides a method of testing a circuit on a substrate. Generally speaking, a substrate is located in a transfer chuck, a surface of a test chuck is moved into contact with a substrate, the substrate is secured to the test chuck, the test chuck is moved relative to the transfer chuck so that the substrate moves off the transfer chuck, terminals on the substrate are moved into contact with contacts to electrically connect the circuit through the terminals and the contacts to an electric tester, signals are relayed through the terminal and the contacts between the electric tester and the circuit, the terminals are disengaged from the contacts, and the substrate is removed from the test chuck.

Abstract: A direct current measuring apparatus includes a voltage generating part generating a voltage to be applied to a load being a measuring object; a current limiting part limiting a current flowing in the load to a set value; and an output terminal connected to the load. The current limiting part includes a D/A converter, a positive side limiting circuit, a D/A converter and a negative side limiting circuit. The positive side limiting circuit includes a negative feedback loop. The negative feedback loop includes a capacitor and a buffer circuit besides the feedback resistance. An output of the positive side limiting circuit positive side limiting circuit is connected to a non-inverting input terminal of the main amplifier through a diode.

Abstract: A device for testing small electronic components includes a test plate for moving a plurality of spaced electronic components to a test station. A roller is designed to press on the test plate and electronic component exerting a first force between 10-20 grams when the test plate and electronic component are moving and exerting a second force of about 50 grams when the test plate is stopped and the electronic component is aligned in the test station. The forces exerted on the test plate and electronic component are controlled by a force-application actuator, such as fluid operated actuator, for example a pneumatic actuator or a solenoid.

Abstract: A wafer-scale probe card for temporary electrical contact to a sample wafer or other device, for burn-in and test. The card includes a plurality of directly metallized single-walled or multi-walled nanotubes contacting a pre-arranged electrical contact pattern on the probe card substrate. The nanotubes are arranged into bundles for forming electrical contacts between areas of the device under test and the probe card. The bundles are compressible along their length to allow a compressive force to be used for contacting the probe card substrate to the device under test. A strengthening material may be disposed around and/or infiltrate the bundles. The nanotubes forming the bundles may be patterned to provide a pre-determined bundle profile. Tips of the bundles may be metallized with a conductive material to form a conformal coating on the bundles; or metallized with a conductive material to form a continuous, single contact surface.

Abstract: A probe card includes a flexible membrane, a plurality of probes attached to the flexible membrane, and a layer of foam connected to the flexible membrane so that when the probes are moved into the flexible membrane, the layer of foam is also deflected to produce a counteracting force at the probes. A plurality of push rods are used to transfer the force at the contacts to the foam layer. The foam layer is attached to a rigid plate or push plate. A guide plate includes openings through which the push rods pass. The guide plate supports the push rods along their length and reduces the spacing between the push rods at the flexible member when compared to the spacing of the push rods at the foam layer.