Patents Examined by Ernest Karlsen
  • Patent number: 7336094
    Abstract: A plurality of individually retractable racks on which a single module is mounted on each rack is disposed on the upper and middle tiers of a portable carriage main body. Provided to the lower tier of the carriage main body are a operating panel for setting work content and conditions; a signal source for selectively outputting a circuit adjustment signal, an aging testing signal, and a display inspection signal; a power supply for circuit adjustment, a power supply for aging testing, and a power supply for display inspection; and an output unit for selecting an operation from circuit adjustment, aging testing, and display inspection on the basis of the work content and work conditions that have been input in the operating panel, and feeding the power and signals for the selected operation to the modules.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: February 26, 2008
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Yuuichi Hasegawa
  • Patent number: 7336066
    Abstract: Testing of an electronic device is carried out by combining power and signal delivery on a single pair of wires. The power delivery is decoupled from the signal delivery, using inductors, so the device power supplied does not interfere with the test signals delivered from the device and the response signals delivered to the device. Further, simultaneous bidirectional signal paths are decoupled, using capacitors, so that the tester transceiver and the device transceiver are not damaged by the power delivered to the device on the same wires. A common fixture may be used to test a number of different types of wafers, independent of the topography, size, or power requirements of the devices on the wafers, resulting in a significant cost saving, because fixture design has become very expensive, in some cases costing more than the tester whose signals it is implemented to deliver.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: February 26, 2008
    Assignee: Credence Systems Corporation
    Inventor: Burnell G. West
  • Patent number: 7336064
    Abstract: The apparatus for measurement of a current which is flowing in an axially elongated electrical conductor at a first electrical potential. The apparatus contains at least one associated sensor element associated with the conductor that is electrically isolated from it at a second electrical potential different from the first electrical potential of the electrical conductor, and having magnetoresistive characteristics. The sensor element is intended to form a loop which is magnetically closed around the conductor in the circumferential direction, with the resistance value being tapped off at axially opposite ends. Its magnetoresistive part is preferably composed of a non-metallic powder composite material with a high magnetoresistive effect.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: February 26, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventors: Klaus Ludwig, Gotthard Rieger
  • Patent number: 7332922
    Abstract: Probes for electronic devices are described. The probe is formed by ball bonding a plurality of wires to contact locations on a fan out substrate surface. The wires are cut off leaving stubs. A patterned polymer sheet having electrical conductor patterns therein is disposed over the stubs which extend through holes in the sheet. The ends of the wires are flattened to remit the polymer sheet in place. The wire is connected to an electrical conductor on the polymer sheet which is converted to a contact pad on the polymer sheet. A second wire is ball bonded to the pad on the polymer sheet and cut to leave a second stub. The polymer sheet is laser cut so that each second stub is free to move independently of the other second studs. The ends of the second stubs are disposed against contact locations of an electronic device, such as an FC chip, to test the electronic device.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: February 19, 2008
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih
  • Patent number: 7332920
    Abstract: A power solid-state device is pulsed from a controlled pulse source, which generates heat in the chip. Similar or identical pulses are applied to a software or equivalent electrical hardware temperature simulator, for predicting the chip temperature. The output of the simulator is monitored, and the controlled pulse source is inhibited in the event that the predicted chip temperature exceeds a limit. A delay may be introduced between the pulse generation and application to the chip. Additional temperatures associated with the chip heat sink may be combined with the chip temperature.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: February 19, 2008
    Assignee: Lockheed Martin Corporation
    Inventor: Gregory A. Arlow
  • Patent number: 7330042
    Abstract: It is an object of the present invention to provide a substrate inspection system, a substrate inspection method, and a substrate inspection apparatus for realizing efficient operation of inspecting both a large region and a small region of a substrate. The present invention includes a first inspection apparatus 11 executing a macro inspection of each of a plurality of substrates 14(l) to 14(n) and outputting information on presence/absence of a defect on each of the substrates; a storage unit 12 storing therein the information on presence/absence of a defect outputted from the first inspection apparatus for each of the substrates; and a second inspection apparatus 13 executing an inspection of a predetermined portion of the substrate. The second inspection apparatus refers to the presence/absence information stored in the storage unit, and inspects a substrate, the one without a defect, of the plural substrates 14(l) to 14(n).
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: February 12, 2008
    Assignee: Nikon Corporation
    Inventors: Kazuhiko Fukazawa, Yasuto Kawashima
  • Patent number: 7330045
    Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 12, 2008
    Assignee: Advantest Corp.
    Inventor: Hideyuki Oshima
  • Patent number: 7330023
    Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: February 12, 2008
    Assignee: Cascade Microtech, Inc.
    Inventors: Randy J. Schwindt, Warren K. Harwood, Paul A. Tervo, Kenneth R. Smith, Richard H. Warner
  • Patent number: 7327154
    Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: February 5, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Gu Shin, Kyoung-Il Heo, Hyoung-Young Lee, Hyuk Kwon, Ki-Bong Ju, Jeong-Ho Bang, Hyun-Seop Shim
  • Patent number: 7323888
    Abstract: A scanning/imaging system wherein an external stimulus is used for exciting a device under test (DUT). A stimulus source is included for providing a stationary stimulus with a controllable spot size to a device under test (DUT), the controllable spot size covering a portion of the DUT for excitation by the stationary stimulus. A sensor is operable for capturing at least one of a functional response signal and an optical image signal emanating from the DUT portion. A linear positioning device is operable to facilitate scanning of remaining portions of the DUT until a predetermined area thereof has been traversed. A controller is operably coupled to the linear positioning device, stimulus source and the sensor for providing the overall control thereof.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: January 29, 2008
    Inventor: James B. Colvin
  • Patent number: 7321232
    Abstract: A charge amount measurement method comprises: interposing a measurement subject between a first substance and a second substance having a through hole; measuring a first collision position where a charged beam passed through the through hole and vicinity of the measurement subject collides against the first substance, in a state that there is no potential difference between the first substance and the second substance, measuring a second collision position where a charged beam passed through the through hole and vicinity of the measurement subject collides against the first substance, in a state that there is a potential difference between the first substance and the second substance, and measuring a charge amount of the measurement subject based on a difference between the measured first collision position and the measured second collision position.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: January 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakazu Hayashi
  • Patent number: 7312624
    Abstract: A substrate for an electro-optical device includes amplifiers each has a first node and a second node, the first node connected to a signal line and being input with a first potential signal, the second node being input with a second potential signal, each amplifier outputting signals such that the potential of the first node is further decreased when the first potential signal is low, and the potential of the first node is further increased when the first potential signal is high. At least two signal lines correspond to at least one of the first and second nodes. A selection unit that selects one signal line. A connection unit connect the selected signal line to at least one of the first and second nodes.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: December 25, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuya Ishii
  • Patent number: 7304487
    Abstract: A contactor apparatus having a first contactor (2) and a second contactor (4) acquires an electrical conduction to a plurality of semiconductor devices formed on a semiconductor wafer (6). The first contactor (2) has contacts (2b) which are directly brought into contact with power supply terminals (6a) of the semiconductor devices. The second contactor (4) is movable relative to the first contactor (2) and has contacts (4a) which are brought into contact with signal terminals (6b) of the semiconductor devices. Thereby, the number of contacts to be formed on a single contactor can be reduced and the number of pattern wirings can also be reduced, which makes the fabrication of the contactor easier.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: December 4, 2007
    Assignee: Fujitsu Limited
    Inventor: Makoto Haseyama
  • Patent number: 7304486
    Abstract: The multi-point probe comprises a supporting body defining a first surface, a first multitude of conductive probe arms each of the probe arms defining a proximal end and a distal end being positioned in co-planar relationship with the first surface of the supporting body. The probe arms are connected to the supporting body at the proximal ends thereof and have the distal ends freely extending from the supporting body, giving individually flexible motion to the first multitude of probe arms. The probe arms originate from a process of producing the probe arms on a wafer body in facial contact with the wafer body and removal of a part of the wafer body providing the supporting body and providing the probe arms freely extending therefrom. The multi-point probe further comprises a third multitude of tip elements extending from the distal end of the first multitude of probe arms. The tip elements originate from a process of metallization of electron beam depositions on the probe arms at the distal ends thereof.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: December 4, 2007
    Assignee: Capres A/S
    Inventors: Christian Leth Petersen, Ulrich Quaade, Peter Folmer Nielsen, Francois Grey, Peter Bøggild
  • Patent number: 7301327
    Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: November 27, 2007
    Assignee: Xilinx, Inc.
    Inventors: Sabih Sabih, Jari Vahe
  • Patent number: 7301361
    Abstract: A logic circuit for board power-supply evaluation to be incorporated into a logic device loaded on a product board includes a circuit that simulates an operation of the logic device so that utilization rate is variable at an arbitrary frequency by use of a predetermined circuit in all available logic elements of the logic device; a circuit that judges normality/abnormality of an operation of the operation simulation circuit; a utilization control circuit that varies and controls utilization rate of the logic device by controlling execution of an operation of the operation simulation circuit based on a judgement result of the operation judgement circuit and sets a utilization rate when the operation simulation circuit is instructed to stop the operation; and a utilization output circuit that outputs the judgement result of the operation judgement circuit and the utilization rate set by the utilization control circuit to the outside.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: November 27, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiyuki Kusano, Mutsumi Shimazaki, Mika Horikoshi, Yasuhiro Yamanaka, Hiroaki Sakai
  • Patent number: 7301326
    Abstract: An apparatus for interfacing a test head to a peripheral system is provided. The apparatus includes a first unit having a first connection member for providing electrical communication with the peripheral system, a second unit having a second connection member for providing electrical communication with the test system, and pivot members coupling the first unit and the second unit. The pivot members enable motion in the following sequence as one of the first and second unit moves towards the other: a) pivotal motion between the first connection member and the second connection member; and b) linear motion which decreases linear distance between the first connection member and the second connection member while maintaining respective contact surfaces of the first and second connection members in parallel.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: November 27, 2007
    Assignee: inTEST Corporation
    Inventors: Roy W. Green, Mark A. Bradford, Davis S. Dao, Trung Van Nguyen, James M. Ogg
  • Patent number: 7298136
    Abstract: An electrical test lead includes an insulated electrical cable having a proximal end and a distal end, an electrical connector disposed at the proximal end of the cable and connected to a test instrument, and an electrically conductive magnetic probe disposed at the distal end. The probe is adapted to magnetically attach to a test point in an electrical system and to provide an electrical connection from the test point through the probe, the cable and the connector to the test instrument. Together, the test lead and the test instrument may be used as an electrical test kit. The test lead may further include an additional electrical test lead component magnetically attached, and electrically connected, to the electrically conductive magnetic probe and extending therefrom. An additional electrically conductive magnetic probe or a non-magnetic electrical connector may be disposed at the distal end of the additional electrical test lead component.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: November 20, 2007
    Inventor: Kevin Mark Curtis
  • Patent number: 7298166
    Abstract: A loading device for conducting a loading test of an objective power source to be tested comprises a rectifier connected to the objective power source to be tested and a resistor connected to the rectifier, the resistor including a retention tank for collecting electrolyte aqueous solution and an electrode member soaked in the electrolyte aqueous solution, a positive electrode of direct current from the rectifier being connected to the retention tank, and a negative electrode of the direct current being connected to the electrode member, and a hydrogen collecting member forming a first space shielded from air being disposed upward in a periphery of the electrode member.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: November 20, 2007
    Assignee: Tatsumi Corporation
    Inventor: Toyoshi Kondo
  • Patent number: 7298155
    Abstract: A probing apparatus includes a mechanism apparatus. The mechanism apparatus includes a base body, a vibration absorber, a shifting mechanism, and a stage connected via the base body to a ground terminal. A probe, positioned over the stage, is connected to a measurement terminal of a measuring apparatus via a signal cable. The signal cable has a connecting terminal connected to the measurement terminal of the measuring apparatus. A shielding cover, positioned over a measured device on a glass substrate held on the stage, has an area not smaller than an area of the measured device and not greater than four times the area of the measured device. The shielding cover is grounded.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: November 20, 2007
    Assignees: Tokyo Cathode Laboratory, Co., Ltd., Agilent Technologies, Inc.
    Inventors: Seiki Fuchiyama, Noriyasu Kiyota, Akito Kishida