Abstract: To limit the current in heavy current testing of semiconductor components with test needles, upstream of each needle a circuit is connected which has low resistance in the range of allowable currents and has high resistance above a given limit current in order to limit the current. The current source which undertakes limitation in the electrical supply lead to the probes is galvanically separated from the voltage supply of the current source itself.

Abstract: An apparatus for automatically displaying a grade of a liquid crystal display device and operating method thereof, includes a grade determining unit of a liquid crystal display panel; a grade inputting unit for inputting the grade of the liquid crystal display panel whose grade has been determined in the grade determining unit; a grade discriminating unit for transferring the grade of a corresponding liquid crystal display panel based upon receiving data input to the grade inputting unit; a storing unit having a grade displaying unit for classifying the graded liquid crystal display panels according to grades and storing the grades; and a robot driving unit for transferring the liquid crystal display panel to the storing unit according to instructions from the grade discriminating unit.

Abstract: A mounting structure for current detection resistor device has a feature that voltage detection terminal wiring is configured so as to extend along a current path in the resistor body first, and then, to bend at right angles to the current path, while maintaining electrical isolation from a resistor body of the current detection resistor device. The voltage detection terminal wiring connecting to the voltage detection terminals on the circuit board is disposed to extend for some distance in the same direction as the current path so as to cause mutual-inductance between that section of the voltage detection terminal wiring and the resistor body. This causes cancellation of induced voltage caused by the self-inductance of the resistor body, so that it is possible to nullify detection error generated by the voltage induced by the resistor body from the viewpoint of the measuring system.

Abstract: According to one embodiment of the invention, a method for estimating the failure rate of semiconductor devices includes obtaining accelerated stress duration data for a plurality of semiconductor devices, determining which of the semiconductor devices fail, classifying the defects for the failed semiconductor devices, determining a distribution model for the accelerated stress duration data, determining a set of parameters for the distribution model, determining a relative proportion of each defect classification to the total number of defect classifications, determining temperature and voltage acceleration factors for each defect classification, identifying actual operating conditions for the semiconductor devices, comparing the actual operating conditions for the semiconductor device with the distribution model, and determining a defect ratio for the semiconductor devices at the actual operating conditions for a predetermined time period based on the comparison.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: A replacement for probe cards includes a full wafer contacter. A first surface of the full wafer contacter is brought into contact with, and the contacter is attached to, a wafer, thereby making electrical connection with at least a portion of the contact pads on each of a plurality of integrated circuits on the wafer. The full wafer contacter provides conductive pathways from the IC contact pads to a second surface of the full wafer contacter where a corresponding set of contact pads provide access to test systems and/or other devices. The contact pads on the second surface of the full wafer contacter are typically larger than the contact pads of the integrated circuits, and are typically spaced father apart from each other. The full wafer contacter is constructed to be suitable to provide access to the contact pads of the unsingulated integrated circuits during a wafer burn-in process.

Abstract: The present invention improves wafer sampling methods by partitioning a semiconductor wafer into a set of sampling regions and calculating yield of a sampling region(s) of the semiconductor wafer.

Abstract: Methods and systems for testing an integrated circuit during an assembly process are described. The integrated circuit is received from inventory. The integrated circuit is placed in a socket on a first circuit board for system-level testing. The system-level testing is performed prior to placement and permanent attachment of the integrated circuit onto a second circuit board. Provided the integrated circuit passes the system-level testing, the placement and permanent attachment of the integrated circuit to the second circuit board is the next step following the system-level testing in the assembly process.

Abstract: A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for electrically engaging terminal contacts on the module with a zero insertion force on the modules. The interface board is configured for mounting to an automated or manual pass through test handler in electrical communication with test circuitry. In a first embodiment the interface board includes test pads in electrical communication with the test circuitry, and rotatable test contactors having spring contacts configured to simultaneously engage the test pads and the terminal contacts on the module. In a second embodiment the interface board includes test pads in electrical communication with the test circuitry, and slidable test contactors having beam leads configured to simultaneously engage the test pads and the terminal contacts on the module.

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace formed on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate and connected to the contact structure through a via hole and the contact trace, a contact target provided at an outer periphery of the contact structure to be electrically connected with the contact pad, and a conductive member for connecting the contact pad and the contact target.

Abstract: An electrical connecting method has the step of bringing a contact member connected to an electric circuit into contact with a terminal of an electronic part. A desired processing is performed by feeding current to the terminal via the contact member. The contact member is then separated from the terminal. When the contact member is brought into contact with the terminal, energy is applied to the contact member or the terminal in order to locally soften a portion of the terminal contacting the contact member. Thereafter, the desired processing is performed, in the state that the contacting portion of the terminal with the contact member is softened so as to reduce the contact resistance and so as to increase the subsequent separatability of the contact member from the terminal.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.

Abstract: The invention relates to a method and an arrangement of testing a device, such as a peripheral device, in a mobile station. The arrangement comprises a signal generator for generating a test signal for the device under test, a measurement unit integrated into the mobile station for measuring en electric quantity from a feeding line of the device under test, and an analyser for determining an electric response of the device to the test signal by using the electric quantity. According to the invention, at least a portion of the testing procedure composed of generating the test signal and determining the electric response of the device is performed using a functional unit, such as the signal generator or the analyser, integrated into the mobile station.

Abstract: A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.

Abstract: The voltage at a node of an integrated circuit can be measured or controlled using a two-wire kelvin contact with spring-based probe pins by offsetting and tapering the lower end section of the spring-based probe pin. As a result, multiple spring-based probe pins can be connected to a single contact bump, such as a solder bump.

Abstract: Circuitry for use in testing a device includes a first measurement unit to apply a forced voltage to the device, and a second measurement unit having functionality that is disabled. The second measurement unit includes a sense path to receive a sensed voltage from the device, where the sense path connects to the first measurement unit through the second measurement unit. The first measurement unit adjusts the forced voltage based on the sensed voltage.

Abstract: An AC voltage generated by an AC power source 1 is rectified by a full-wave rectifying circuit 2, which generates a rectified voltage. An internal regulator 33 performs waveform shaping of the rectified voltage. A comparator 42 compares the rectified voltage output from the internal regulator 33 with a reference voltage V1 and detects a period in which the rectified voltage exceeds the reference voltage V1. According to an output signal of the comparator 42, a determination signal generation circuit 50 determines the power source voltage supplied form the AC power source 1 and generates a determination signal. Accordingly, there is no need of a capacitor, etc. for detecting the peak value of the rectified voltage, and it is possible to reduce the size and cost of an AC voltage detection circuit.

Abstract: A chuck adapted to test electrical and/or optical components on a device-under-test (DUT).

Abstract: A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate on the interface board. The interface board includes interface contacts in electrical communication with external test circuitry. The substrate includes flexible segments, and contactors having contact pads on opposing sides of the flexible segments configured to simultaneously electrically engage terminal contacts on the components, and the interface contacts on the interface board. The contact pads include conductive polymer layers that provide an increased compliancy for the contactors. This increased compliancy allows the contactors to accommodate variations in the dimensions and planarity of the terminal contacts on the component. In addition, the substrate includes grooves between the contactors which provide electrical isolation and allow the contactors to move independently of one another.