Abstract: An integrated current sensor includes a magnetic field transducer such as a Hall effect sensor, a magnetic core, and an electrical conductor. The conductor includes features for receiving portions of the Hall effect sensor and the core and the elements are dimensioned such that little or no relative movement among the elements is possible.

Abstract: The invention provides a method of testing a circuit on a substrate. Generally speaking, a substrate is located in a transfer chuck, a surface of a test chuck is moved into contact with a substrate, the substrate is secured to the test chuck, the test chuck is moved relative to the transfer chuck so that the substrate moves off the transfer chuck, terminals on the substrate are moved into contact with contacts to electrically connect the circuit through the terminals and the contacts to an electric tester, signals are relayed through the terminal and the contacts between the electric tester and the circuit, the terminals are disengaged from the contacts, and the substrate is removed from the test chuck.

Abstract: A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipment, and also reducing signal delay and distortion. A system in accordance with the present invention includes a circuit board having circuitry adapted to provide an actual operating environment for the semiconductor device, as for example, a low cost mother board for testing memory devices. The device is coupled to the back side of the circuit board through test terminals formed on the back side of the board. An interface board can be used to correct the pin arrangements, which are reversed because they protrude from the back side of the board, and to compensate for the environmental differences caused by use of sockets and additional equipment on the interface board.

Abstract: The present invention provides a method of electron beam testing of liquid crystal displays comprising non-uniform electrodes having a conductive portion and a dielectric portion. In accordance with methods of the present invention, the diameter of the electron beam is increased so that the beam is less focused, i.e., enlarged or “blurred,” over a non-uniform electrode area. The diameter of the beam is increased so that the beam generates secondary electrons from the conductive portion of the non-uniform electrode area. The configured test beam may be circular, elliptical, or other suitable shapes.

Abstract: A sensor apparatus is for a power bus including a plurality of characteristics. The sensor apparatus includes a housing; one or more sensors each adapted to sense a characteristic of the power bus; and a circuit adapted to transmit or receive a wireless signal. A processor includes a low-power mode and a routine adapted to wake up from the low-power mode, to input the sensed characteristic from the one or more sensors, to output a corresponding signal to the circuit to transmit as the wireless signal, and to sleep in the low-power mode. A power supply is adapted to power the sensors, the circuit and the processor from flux arising from current flowing in the power bus. The power supply includes one or more voltages.

Abstract: Wafer-level testing is performed on an electronic device to be used in an optical communications system. An optical test signal is generated and is provided to a first photo detector. An electrical output of the first photo detector is supplied to the electronic device on the wafer. An electrical output from the electronic device on the wafer is used to drive a light source. An optical output of the light source is supplied to a second photo detector and an electrical signal output from the second photo detector is examined.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A probe retention kit may include a plurality of probe retention devices, each having: (i) a base; (ii) a retention mechanism, coupled to the base, for mechanically coupling a probe substrate with the plurality of probe retention devices; and (iii) solder legs to be inserted into a printed circuit board, the solder legs having opposite ends that extend through the base and provide an alignment mechanism for receiving the probe substrate. Alternative probe retention devices, and systems and methods using same, are also disclosed.

Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

Abstract: A probe includes an electrical element. The probe has reduced parasitic loading. A probe assembly with a plurality of probes is also disclosed.

Abstract: An electronic energy meter senses input voltage and current signals and processes the input voltage and current signals to generate measurements of multiple types of power. The meter comprises a processing system for selecting one of the multiple types of power and defining the same as the selected type of power. The processing system also generates a pulsed test signal representative of a magnitude of a measurement of the selected type of power for testing the operation of the meter. The meter further comprises a communications interface coupled to the processing system for transmitting the pulsed test signal from the meter and for receiving signals from sources external to the meter. Selection of one of the multiple types of power can be achieved by the meter receiving, via the communications interface and from a source external to the meter, a communications command identifying a selected one of the various types of power. The communications interface may comprise an optical communications port.

Abstract: A system for testing electronic modules comprising at least one mapping board box, and at least one harness operably attached to the mapping board box with a harness port is disclosed. The mapping board box comprises pin receptors, wherein the receptors are in communication with a pinned circuit board to comprise a system for testing electronic modules. The mapping board box is pre-wired to receive circuit boards with a variety of pin configurations.

Abstract: Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract: The present invention determines temperature and current from resistance measurements of a single magnetoresistive sensor. A dual-purpose sensor includes the magnetoresistive sensor having a single pair of terminals. The sensor is multiplexed under separate current conditions to produce both a temperature measurement and a current measurement in a vicinity of the sensor. A sensor system includes the dual-purpose sensor, a resistance sensing subsystem and a controller that controls the current conditions. A method of measuring temperature and current includes measuring a first resistance of the dual-purpose sensor while a first current is flowing in a conductor adjacent to the sensor, and measuring a second resistance of the sensor while a second current is flowing in the conductor. The first current has a known value while the second current has an unknown value. The temperature and current are determined respectively from the first and second resistance measurements.

Abstract: An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage extends through a portion of the housing and connects to the chamber thus permitting passage of a fluid material into the chamber. At least one contact member is positioned on the flexible membrane so as to provide an electrical connection to an electrical contact on a device to be tested.

Abstract: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.

Abstract: A probe card includes a flexible membrane, a plurality of probes attached to the flexible membrane, and a layer of foam connected to the flexible membrane so that when the probes are moved into the flexible membrane, the layer of foam is also deflected to produce a counteracting force at the probes. A plurality of push rods are used to transfer the force at the contacts to the foam layer. The foam layer is attached to a rigid plate or push plate. A guide plate includes openings through which the push rods pass. The guide plate supports the push rods along their length and reduces the spacing between the push rods at the flexible member when compared to the spacing of the push rods at the foam layer.

Abstract: An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures.

Abstract: A test device includes first and second testers each having at least one testing contact for making contact with at least one external contact of an electronic component; and a conveying device that conveys electronic components to the first and second testers in a synchronized manner such that the external contacts of the electronic components form an electrical connection to the testing contacts. Via the testing contacts, it is possible to apply input voltages and input currents to the electronic components and it is possible to measure the voltages, currents and resistances prevailing in the electronic components. The testers check the electronic components on the basis of a predetermined overall set of test criteria or on the basis of subsets of the overall set of test criteria.

Abstract: A probe card for production testing of semiconductor imaging die includes a stiffener supported on a bottom side of the probe card. The top of the stiffener is substantially flush with a top surface of the probe card. A light passage through the stiffener features non-reflective surfaces. Surfaces surrounding the light passage are arranged to avoid casting any shadows on the imaging die being tested. The arrangement provides a low profile probe card. A source of light used to illuminate the imaging die through the light passage can be placed close to the imaging device under test, providing few false negatives and more consistent results from wafer to wafer.