Abstract: A user PC 20 prepares a retrieve request by storing a SNMP command and a predetermined processing execution condition into a retrieve request of a SLP and transmits and outputs the prepared retrieve request to a printer 40 and others by multicast. Receiving the retrieve request, the printer 40 obtains and executes the SNMP command stored in the retrieve request of the SLP and processes a response to the retrieve request when the execution result meets the processing execution condition. Thus, the SNMP command is executed by receiving the retrieve request of the SLP and the response to the retrieve request of the SLP is processed corresponding to the execution result, it is not necessary to separately transmit or to obtain the request process of the SLP and the retrieve request of the SNMP through the network and the execution result of the SNMP command may be reflected to the process of the SLP.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.

Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

Abstract: The peripheral device management system includes a server, a peripheral device, a data processing device. The data processing device includes an attempting unit, a confirming unit, a notifying unit, a first setting unit, and a second setting unit. The attempting unit attempts to acquire, from the peripheral device, firmware data. The confirming unit confirms, to the server, whether a newer firmware than the firmware installed on the peripheral device is available for downloading from the server. The notifying unit notifies that the newer firmware is available for downloading from the server. The first setting unit sets a first confirmation time as the confirmation time if a result of the attempting unit satisfies a prescribed condition. The second setting unit sets a second confirmation time that precedes the first confirmation time as the confirmation time if the result of the attempting unit does not satisfy the prescribed condition.

Abstract: A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attribute out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attribute different from the attribute in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined.

Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

Abstract: A programmable system includes programmable analog and digital components that, when configured by a processing device, implement a line driver to transmit differential signals over multiple drive lines and a line receiver to receive differential signals over multiple receive lines. A system includes a line receiver to receive differential signals from receive lines with multiple input pads and to convert the differential signals into a single-ended signal. The system further includes a digital communication device to receive the single-ended signal from the line receiver and extract received data from the single-ended signal. The system includes a line driver to receive transmission data from the digital communication device, convert the transmission data into differential signals, and provide the differential signals to multiple output pads for transmission over drive lines.

Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: A data center has several dis-aggregated data clusters that connect to the Internet through a firewall and load-balancer. Each dis-aggregated data cluster has several dis-aggregated compute/switch/disk chassis that are connected together by a mesh of Ethernet links. Each dis-aggregated compute/switch/disk chassis has many processing nodes, disk nodes, and I/O nodes on node cards that are inserted into the chassis. These node cards are connected together by a direct interconnect fabric. Using the direct interconnect fabric, remote I/O and disk nodes appear to the operating system to be located on the local processor's own peripheral bus. A virtual Ethernet controller and a virtual generic peripheral act as virtual endpoints for the local processor's peripheral bus. I/O and disk node peripherals are virtualized by hardware without software drivers. Rack and aggregation Ethernet switches are eliminated using the direct interconnect fabric, which provides a flatter, dis-aggregated hierarchy.

Abstract: The invention discloses a method and system for implementing automatic installation of a key device, and relates to the field of smart card. The method includes steps of: establishing, by the key device, a connection with a computer; declaring to the computer that the key device itself is a compound device containing a USB keyboard device; sending a predefined first keyboard message sequence to the computer, wherein the first keyboard message sequence is used for starting an operation environment of the computer; converting, after the operation environment is started, a pre-stored script instruction for running an installation program into a second keyboard message sequence, and sending the second keyboard message sequence to the computer; sending a predefined third keyboard message sequence to the computer, wherein the third keyboard message sequence is used for running the installation program. The system includes a key device and a computer.

Abstract: An information processing apparatus includes a communication processing unit configured to communicate with an external communication device and a data processing unit configured to communicate with the communication processing unit via a wired data communication path. The data processing unit is configured to interpret address information received from the external communication device. The communication processing unit includes a memory where data transmitted and received between the external communication device and the data processing unit is temporarily stored. The communication processing unit further includes a control unit configured to control data writing in and data reading from the memory, perform an error check process by a code included in a received data from the external communication device, and transmit the address information received from the external communication device to the data processing unit without interpreting the address information.

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract: A data transfer control device includes a control component (DMA controller 5) which acquires a data transfer instruction including, as its parameters, start memory addresses or start input/output addresses and data transfer size of the peripheral devices to be used as the transfer source and transfer destination when carrying out data transfer from a first peripheral device (peripheral (A)) to a second peripheral device (peripheral (B)); which reads out target data from the first peripheral device in accordance with the parameters; and which processes the target data and then transfers to the second peripheral device.

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

Abstract: This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.

Abstract: In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses of the electrical components determine a position of an electrical component with respect to the other of the electrical components in the daisy chain.

Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.