Abstract: A method and system for the synchronization of the transmission of digitally converted analog modem signals between two or more modems using either RF over-the-air or A/C power line communication channels. This invention provides for modem speed optimization by minimizing or eliminating clock variance between the modems in a digital communication system. A fixed delay is created and maintained during modem operation. This invention is also adapted to function in a full-duplex communication system maintaining a fixed delay in both directions.

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over a an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems.

Abstract: A digital baseband (DBB) radio frequency (RF) receiver includes a digital high pass filter compensation (HPFC) module used to suppress group delay variation distortion caused by using low cost analog high pass filters (HPFs) in the receiver. The digital HPFC module reduces a cutoff frequency, established by the HPFs for the real and imaginary signal component frequency domain responses by providing a first compensation signal having a first predetermined value (K1). The digital HPFC module adjusts the gain of the high pass response of the real and imaginary signal component frequency domains by providing a second compensation signal having a second predetermined value (K2).

Abstract: A waveform equalizer having a delay element of a feed-forward filter into which a reception signal is inputted is connected via a tap arrangement control switch to a weighting device The output of the weight device is inputted into an adder. The output of the adder is entered into a discriminator to become an equalization output. The equalization output is entered into a delay element of a feed-back filter. The delay element is connected via the tap arrangement control switch to the weighting device. The tap arrangement control switch ON/OFF-controls the tap arrangement. The tap coefficient monitoring unit monitors the tap coefficients of the weighting device. When the equalization operation cannot be carried out, it is restarted from the beginning of the reception signal. An impulse response predictor predicts an impulse response of a transfer path based upon the reception signal and the equalization output.

Abstract: The present invention relates to a device and method for injecting a noise signal into a wire pair of a communication link. In operation a differential mode noise signal is received at a first and a second input port, which are connected via a first and a second resistor to a first and a second end tap of a primary coil of a transformer, respectively. The transformed differential mode noise signal is then transmitted via a first and a second end tap of a secondary coil of the transformer and a third and a fourth resistor to a first and a second output port for injection at high impedance into a first and a second wire of the communication link. Optionally, the device comprises a third input port connected to a center tap of the secondary coil for receiving a common mode noise signal. The common mode noise signal is then provided at low impedance to the first and the second wire via the first and the second end tap of the secondary coil and via the third and fourth resistor having low impedance, respectively.

Abstract: A baseband digital signal block is processed at an output of a matched filter and at an input of a channel equalizer. This signal is fed to a whitening filter estimated for the block by taking into account interfering signals in the frequency band of the useful signal and in one or more adjacent bands. To this end, an autocorrelation vector, calculated form the block of received signal is projected onto different directions corresponding to predetermined correlation vectors relating to the useful signal, to signals which may be present in the adjacent bands and to the thermal noise. The coefficients of the whitening filter are then derived from the sum of the projected vectors, by taking into account the energy of the useful signal if the latter has not been cancelled prior to the computation of the autocorrelations.

Abstract: The invention relates to a method for synchronizing a receiver (1) with a transmitted code-modulated spread spectrum signal. The method uses at least one reference code (r(x)), which corresponds to a code used in the modulation. The frequency shift of the transmitted signal and the code phase of the code used in the modulation are determined in the method.

Abstract: A system and method for the automatic establishment of a connection between a human interface device and a host transceiver unit, wherein the system includes a host transceiver unit configured to be connected with a host via a bus, and configured to wirelessly exchange data with a human interface device; a human interface device configured to wirelessly exchange data with a host transceiver; and a computer readable media having instructions thereon, wherein said instruction include routines for synchronizing the host transceiver unit and the human interface device for wirelessly exchanging data between the host transceiver unit and the human interface device at a spread spectrum modulation pattern which is determined by the host transceiver after the host transceiver unit and the human interface device have acknowledged each other's presence.

Abstract: The invention relates to a method and a radio system for transmitting a digital signal. The method comprises the following steps: the transmitter transmits at least a part of the signal via at least two different transmit antenna paths; the transmitter weights the transmit power of the signals to be transmitted via the different transmit antenna paths with respect to one another by means of changeable weighting coefficients determined for each transmit antenna path; the receiver receives the signal.

Abstract: The communication system includes two communication channels for communication of protection and control information between two protective relays on a power line portion of an electric power system. A switch provided at the receiving relay connects one communication channel and provides a connecting link between the communication channel and the receiving relay. The transmitted data is applied on both communication channels and processed substantially identically. When the one communication channel is indicated to be faulty, the switch in the receiving relay is operated to connect the second communication channel, thereby substantially preventing delay in the receipt of the data from the transmitting relay.

Abstract: A receiver receives elements of a signal sequence. A state generator generates a sequence of addresses to translate between a pseudonoise sequence and a Walsh sequence. A storage medium, coupled to the receiver and the state generator, stores each element of the signal sequence at a given address according to the sequence of addresses.

Abstract: A method for high-frequency signal transmission between a transmitter and a receiver. A signal for generating a natural electromagnetic alternating field is linked with HF transmission signal, and the HF transmission signal is extracted from the linked signals.

Abstract: A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.

Abstract: A system is provided for synchronizing a PSTN clock and a DSL clock. The system comprises a PSTN interface for transmitting and receiving voiceband samples, a data DSL transceiver for modulating and demodulating data to and from DSL samples, a synchronization circuit for synchronizing the voiceband samples and the data samples, and a converter for converting the synchronized voiceband and DSL samples between analog and digital formats. The synchronization circuit synchronizes the voiceband and the data samples for conversion by the same converter.

Abstract: The invention relates to a method and device for estimating an estimated value (U2max) dependent on the maximum (Umax) of a single-frequency signal sampled via a succession of sampled values (d(n)), wherein each of a predetermined number (N) of sampled values (d(n)) is squared and the predetermined number (N) of squared sampled values (d2(n)) is summated.

Abstract: A desired bit sequence (x) can be communicated over a wireless communication link (15) by including the desired bit sequence in each of a plurality of transmissions over the wireless communication link. In response to each of the plurality of transmissions, a received bit sequence corresponding to the desired bit sequence can be produced at the receiving end. A determination of the desired bit sequence can be made based on the received bit sequences (r1–rN) and information (SNR1–SNRN, ?1–?N) indicative of communication quality associated with each of the plurality of transmissions.

Abstract: The present invention provides a system and method for implementing a new TEQ training approach that trains TEQ coefficients by exploiting both time-domain and frequency-domain information. An advantage of this technique is that it reduces memory usage due to the training process. In addition, the complexity of the training process is simplified, and the associated computational work is reduced. The reduction of memory usage and computational work in turn may lead to cost savings, power consumption savings and other advantages.

Abstract: Errors are reduced when tracing PRNS code delay, especially in receivers operating on signals with rather low code frequency (C/A code) under multibeam effect without deterioration or with minimum deterioration of the signal-to-noise ratio. A method of increasing noise immunity during reception of signals from satellite navigational systems and a device for realizing the same includes radio modules, an analog-to-digital converter, a digital correlation device and digital correlators. A discrimination signal is generated with a variable delay of the signal copy with respect to the exact copy. The use of the correcting sequence of gating digital signals makes it possible to eliminate the multipath effect at a delay of the reflected signal larger than 1.5 d and reduces its negative effect starting from a delay value greater than d/2. In this case, the energy losses compared with a pure mode of the narrow correlator are increased only by 1.76 dB.

Abstract: A region searcher, a method of driving the same, and a code searcher using the same are disclosed. When a predetermined region is iteratively searched, the energy value corresponding to the same hypothesis location value is stored by using a searcher having divided two buffers, thereby the implementation complexity thereof can be remarkably reduced, without using a simple memory. In addition, in case where the region is iteratively searched in the state of the deteriorated signal-to-noise ratio to find the energy value at one hypothesis location and in case where the region must be iteratively searched because of the restriction which the size of the matched filter can be not increased, the implementation complexity thereof can be remarkably reduced.

Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.