Abstract: There is provided a digital data receiver for recovering at least one message word signal from a digital data frame.

Abstract: A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator programmable so as to allow the operator to input the test data values. The data transceiver further includes a transmitter section coupled to the self-test data generator, a receiver section coupled to the transmitter section, and a test data analyzer coupled to the receiver section, wherein the test data analyzer includes a second pseudo-random number generator, which allows the operator to input the data value via a data bus coupled to the test data analyzer. Both the self-test data generator and the test data analyzer are independently controllable.

Abstract: A simplified, weak GPS C/A code coherent acquisition method. When performing GPS signal acquisition, the strength of a signal received at a GPS receiver having an outside antenna is generally sufficiently strong such that only 1 ms of data needs to be used in acquisition to find the signal. However, for weak signals received at a GPS receiver, when the antenna is inside a building or vehicle, for example, a long record of data is needed for acquisition. The present invention reduces the calculation burden for GPS signal acquisition for a weak signal.

Abstract: According one embodiment, an apparatus and method are disclosed for a dynamic phase aligning input interface. In the embodiment, a first device provides data to a second device. According to the embodiment, the interface is counter clocked, the second device being clocked by a first clock signal and providing a second clock signal source to the first device for clocking the data. The first device transmits the second clock signal and the data to the second device, with the second clock signal being delayed by the period of time required for the second clock signal source to propagate through the first device. The second device detects the phase of the first clock signal and the second clock signal and modifies the phase of the second clock signal source to align the phase of the first clock signal and the phase of the second clock signal.

Abstract: A method of baseband/passband digital modulation for a data transmission system wherein a plurality of data symbols is transmitted over a transmission channel at a symbol rate. The method comprises the following steps: (1) generating a plurality of I and Q components of symbols by mapping an input bit stream comprising a plurality of digital codewords into a QAM constellation; (2) selecting a passband or a baseband mode; and (3) generating an analog output signal in the passband or baseband mode. The step of selecting the passband or the baseband mode depends on the complexity of QAM constellation. If QAM constellation includes less than 64 QAM plant points, the passband mode is selected, and if QAM constellation includes more than 64 QAM plant points, the baseband mode is selected.

Abstract: An arrangement for capturing data from a data stream of a predetermined data transfer rate using a flip-flop, comprises a symmetrical multi-phase clock generator that is adapted to be locked to a reference clock which in turn is adapted to generate a reference clock signal at the data transfer rate or at a fraction thereof. The multi-phase clock generator is adapted to generate “n” clock signals mutually shifted in phase 360°/n from each other. A selector is connected to the clock generator to receive the n clock signals and selects one of these n clock signals as the system clock signal in response to a control signal from a clock phase counter. The clock phase counter is controlled to count up or down in response to the phase of the system clock signal when a predetermined number of data transitions have occurred in the data stream. The flip-flop is controlled by the opposite phase of the system clock signal to capture the data from the data stream.

Abstract: A detector receives a signal and detects from it a long code composed from shorter codes, where the shorter codes are dithered according to a non-repeating dither pattern. The received signal is correlated with a reference code, the correlation sums are ranked, and short codes detected from the ranked sums. Because of a high jamming to signal (J/S) ratio, all the transmitted short codes may not be detected. A dither matching algorithm determines an interval between the detected codes and matches it with a previously stored dither pattern. If there is a strong match, the correlation sums and respective receive times are stored in a hypothesis data structure. If enough subsequent correlation pair have similar matches to exceed a threshold, the match is declared correct and the results are output. The time difference between received and matched pairs can be a measure of a pseudorange between transmitter and receiver.

Abstract: A method of enhancing signal tracking in a global positioning system receiver utilizing a frequency banked filter in providing code and carrier tracking loops includes acquiring a continuous time global positioning signal and separating the continuous time global positioning signal into in-phase and quadrature signals I and Q. The signals I and Q are sampled over a predetection interval (PDI) to provide discrete time signals, and the discrete time signals are used to generate a component in-phase measurement and a component quadrature measurement for each of multiple PDI segments of one PDI. For each of multiple different frequency bins, composite in-phase and quadrature measurements are generated by combining component in-phase measurements and component quadrature measurements from the PDI.

Abstract: An interleaved coding method can be used in a transmitter, in which the two or more pseudonoise (PN) codes are interleaved to form a longer interleaved code. The method can be used in a transmitter that includes a first code generator generating a first code of n symbols, and a second code generator generating a second code of m symbols, where n and m can be mutually prime, such as m=n+1. An interleave unit is coupled to the first and second code generators, and interleaves the symbols of the first code with the symbols of the second code to output an interleaved code. The interleaved code has a period longer than either of the constituent PN codes, providing for much increased noise tolerance over using the short codes alone, and can be detected at a much lower hardware and time cost than if using a single PN code of equal length.

Abstract: A method for bi-directional data synchronization between different clock frequencies is described wherein a state machine counter is provided a first clock signal having a first frequency. The state machine counter is then provided a second clock signal having a second frequency that is an integer multiple of the first clock frequency. The state machine counter has an integer number of states equivalent to the ratio of the second clock signal frequency to the first clock signal frequency. The first clock signal is applied to reset the state machine counter to an initial state. The state machine counter generates an intermediate clock signal whenever the state machine increments through all states to return to the initial state. The intermediate clock is then applied to synchronize data between the first clock frequency and the second clock frequency.

Abstract: A delayed decision feedback sequence estimation diversity receiver includes a section for extracting a plurality of reception signals by using a plurality of antennas when estimating a transmission signal from reception signals having undergone transmission path distortion, a section for combining impulse response sequences in transmission paths while canceling delayed wave components having the largest amplitudes in delayed wave component sequences in impulse response sequences in the respective transmission paths, and a section for performing signal estimation on the basis of a new impulse response sequence generated by combining the impulse response sequences. A delayed decision feedback sequence estimation method is also disclosed.

Abstract: A clock signal recovery circuit that is implemented in a receiver of a universal serial bus (USB) and a method for recovering a clock signal. The clock signal recovery circuit comprises a phase detector, a bidirectional shift register, a multiphase clock signal generator, and a phase selector. The phase detector detects a difference in phases between received data and a predetermined recovery clock signal and generates a first control signal indicative of the detected phase difference. The shift register is shifted in response to the detected signal and outputs a second control signal.

Abstract: A demapping system and method for demapping symbols into bits, is provided. An embodiment of the system comprises a processor, and a memory that is coupled to the processor. The memory comprises a memory module that comprises a program that finds a hard demapper output d based on a received symbol r; finds a challenger ci for each i, the challenger ci is a challenger of the hard demapper output d, i is an integer whose maximum value is a number of bits of the challenger ci; calculates reliability mi for each i, the reliability mi is the reliability of the hard demapper output d; and calculates soft bit xi for each i, the soft bit xi is calculated based on the reliability mi.

Abstract: A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator, an IQ balancer, and a latency time delay device. The latency time delay device delays I and Q signals by a latency time period. During the latency time the IQ coefficient calculator uses the I and Q signals during a section of the packets corresponding to the latency time period for computing correction coefficients. The IQ balancer receives the I and Q signals after the latency time period and applies the correction coefficients to the entire packet of I and Q signals.

Abstract: Method and apparatus for performing joint timing recovery in a digital receiver using multiple input signals. The apparatus comprises a plurality of phase detectors, a summer, a level shifter, a loop filter and a numerically controlled oscillator NCO. The phase detectors produce a phase signal by comparing a timing signal produced by the NCO with the input signals. The phase signals are then summed and the level shifter adjusts the summed value to compensate for the number of signals used to form the sum, i.e., the summed value is adjusted to be within the input range of the NCO.

Abstract: A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes a set of correction coefficients for each packet from the I and Q signals in an IQ measurement section at the front of the packet. The IQ balancer uses the correction coefficients for correcting the I/Q gain and I/Q phase errors on a packet-by-packet basis. Optionally, delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section.

Abstract: A device includes a request arbitration unit that (1) receives a number of requests for PN vectors from a number of processing units and (2) provides a control indicative of each request selected for processing. An address generator provides one or more addresses (which may be dependent on a particular PN sequence being requested and the offset of the PN sequence) for each selected request. One or more memory units store all “base” PN sequences (e.g., and X(i) sequence and a Y(i) sequence defined by W-CDMA) that may be used to generate all requestable PN vectors. The memory unit(s) provide one or more segments of one or more base PN sequences, based on the address(es). A buffering unit provides a set of one or more PN vectors derived from the one or more PN segments for each selected request.

Abstract: The invention describes a method and a system for fast and economic synchronization of multiframe structures, such as PDH multiframe binary signals, by detecting a periodic binary signature in a binary signal using one final state machine (FSM) comprising a logical scheme interconnected with a memory block having a plurality of independent memory cells with serial numbers for cyclically connecting thereof to the logical scheme; the signature is detected by applying the signal to the FSM while synchronously switching the cells to the FSM. The arrangement is such that when the predetermined periodic binary signature occurs in the signal, one of the cells will reach its predetermined terminal state.

Abstract: A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain signals for optimally combining the receiver chain signals in a composite equalized signal and uses noise-based time-varying postscaling the equalized signal. The receiver determines noise-based scale factors by comparing signal symbols to dispersed replica symbols of a training sequence for the incoming signal.

Abstract: A digitally implemented demodulator. A frequency-modulated signal is applied to a limiting amplifier such that the signal amplitude is fixed at a constant level. The signal is undersampled and quadrature demodulated. The demodulator generates the cross-product of the baseband complex envelope to recover the original modulating signal. A digital Frequency Shift Keyed signal can be further recovered by applying the recovered signal to a data slicer to square-up the signal, and a matched filter for improved error resistance.