Patents Examined by Eva Zheng
  • Patent number: 7054376
    Abstract: A facility transport system for transporting high speed Ethernet data over digital subscriber lines. The system, referred to as 100BaseS, is capable of transmitting 100 Mbps Ethernet over existing copper infrastructure up to distances of approximately 400 meters. The system achieves bit rates from 25 to 100 Mbps in increments of 25 Mbps with each 25 Mbps increment utilizing a separate copper wire pair. Each pair used provides a bidirectional 25 Mbps link with four copper wire pair connections providing 4×25 Mbps downstream channels and 4×25 Mbps upstream channels. The system utilizes framing circuitry to adapt the 100BaseT input data signal to up to four separate output signals. A DSL Ethernet Port card couples the modem to each twisted pair used. Each DSL Ethernet Port card comprises modem transmitter and receiver circuitry for sending and receiving 100BaseS signals onto twisted pair wires.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: May 30, 2006
    Assignee: Infineon Technologies AG
    Inventors: Avinoam Rubinstain, Yackov Sfadya, Shimon Peleg, Noam Alroy, Amnon Harpak, Boaz Porat
  • Patent number: 7054346
    Abstract: A wireless endpoint employs frequency hopping for communicating signals in a wireless communications system. Over a time period T, the wireless endpoint performs pseudo-random selection of a frequency from a hopping set of N frequencies such that over at least a portion of the time period T, the frequency selection is constrained to less than the N frequencies.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: May 30, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Krishna Balachandran, Joseph H Kang, Kumud K Sanwal, James Paul Seymour
  • Patent number: 7054352
    Abstract: A CDMA mobile telephone allowing the drive mode to be automatically set and canceled without increasing the amount of hardware is disclosed. A frequency offset for each of N fingers is detected from despread data which are obtained by despreading received spectrum-spread data of M branches. Based on the detected N frequency offsets, it is determined whether the mobile telephone is moving at speeds higher than a predetermined speed. An operation mode of the mobile telephone switches between a drive mode and a normal mode depending on whether the mobile telephone is moving at speeds higher than the predetermined speed.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 30, 2006
    Assignee: NEC Corporation
    Inventor: Osamu Hasegawa
  • Patent number: 7050488
    Abstract: PL demodulation section 203 demodulates pilot signals of a received signal. SIR detection section 205 detects the reception quality of the demodulated pilot signals. fd detection section 206 detects a Doppler frequency using the demodulated pilot signals. Requested modulation method deciding section 207 decides a modulation method to be requested to the base station using the reception quality of pilot signals and the detected Doppler frequency. Command generation section 208 generates a command corresponding to the decided modulation method. Adaptive demodulation section 204 performs demodulation processing on the received signal using the demodulation method corresponding to the modulation method decided by requested modulation method deciding section 207. This makes it possible to maintain good reception quality even in a fading environment.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Miyoshi, Katsuhiko Hiramatsu
  • Patent number: 7042938
    Abstract: Method and apparatus for soft bit computation with a reduced state equalizer. The method assures that the number of states in the equalizer is reduced to obtain acceptable complexity, while also ensuring that soft bit computation is performed for substantially all bits. The method involves computing a first set of soft bits from bits transmitted in a received signal, using a reduced-state trellis with finite non-zero delay, calculating hard decisions in response to the received signal, and also ensuring that substantially all soft bits are computed by employing zero-delay soft decision-making or decision-feedback equalization to compute a second set of soft bits. Furthermore, the hard decisions are used to compute the second set.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: May 9, 2006
    Assignee: Nokia Corporation
    Inventors: Andrei Malkov, Heikki Berg, Pekka Kaasila, Kiran Kumar Kuchi, Jan C. Olivier
  • Patent number: 7039123
    Abstract: A demodulation method, and apparatus, for reproducing data from a received signal. The demodulation method includes the steps of: receiving a signal including a series of frames each containing a training signal for automatic equalization processing and a data signal; controlling an amplitude of the received signal by AGC processing so as to make the amplitude a predetermined level; conducting demodulation processing on the signal subjected to the AGC processing; periodically conducting automatic equalization processing so as to adapt the modulated signal to characteristics of the signal transmission path based on each training signal of the frame; and setting values of a time constant of the AGC processing and an update repetition period of the automatic equalization processing so as to satisfy a predetermined relation.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: May 2, 2006
    Assignee: Hitachi Koksusai Electric, Inc.
    Inventors: Yoshiro Kokuryo, Kunihiko Kondo, Hiroyuki Ando, Nobuo Hirose
  • Patent number: 7031419
    Abstract: The invention relates to a data transmission system between two transceivers, including: dividing the symbols to be transmitted into blocks, the number of which is divisible by the number of transmitting antennas; transmitting one block using each antenna; receiving the blocks using one or more antennas; checking whether the blocks were received successfully; and, if the reception of the blocks failed, storing the received blocks in memory; retransmitting the same blocks in a predetermined format; receiving the retransmitted blocks and combining them with the blocks in memory, the predetermined format being selected in the method so that the blocks transmitted first and the retransmitted blocks form space-time block coding.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 18, 2006
    Assignee: Nokia Corporation
    Inventor: Olli Piirainen
  • Patent number: 7027525
    Abstract: The invention relates to AC coding. The phase angle or the duration of pulses are marked by half-periods or periods and are then provided as stages. The aim of the present invention is to flexibly adjust the bandwidths and bit rates. The number of filler elements that are allocated to the active code elements is increased or reduced. Bit rate flexibility is obtained by increasing or reducing the positions or stages or by configuring the code elements of virtual code words in a serial manner in relation to code words for transmitting information, whereby said code elements are arranged in parallel.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: April 11, 2006
    Inventor: Josef Dirr
  • Patent number: 7020181
    Abstract: The present invention provides a code division multiple access receiver which can maintain the accuracy of the result of demodulation of a received signal at a good level without increasing the scale of circuits and the amount of computation. In the code division multiple access receiver, a control section 14 outputs amplitude-adjusting signals corresponding to the reception level of a received base band signal to an amplitude-adjusting section 20, and the amplitude-adjusting section 20 performs bit operation processes for removing invalid bit data from the complex correlation results of the received base band signal based on the amplitude-adjusting signals.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: March 28, 2006
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Hisashi Kawai
  • Patent number: 7020191
    Abstract: A network device monitors a signal transmitted to a wireless or optical link and a signal received from the link for detecting a bit-by-bit coincidence between them. In response to the detection of the coincidence, the network device determines that the received signal is a copy of the transmitted signal. The network device further monitors its transition states for detecting a predetermined state which would persist indefinitely during a link failure. When the predetermined state and the copy of the transmitted signal are simultaneously detected, the network device discontinues its predetermined state and enters a normal state.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: March 28, 2006
    Assignee: NEC Corporation
    Inventor: Takayuki Nyu
  • Patent number: 7012971
    Abstract: A channel quality assessment with short assessment time and good frequency resolution is disclosed. Some channels are grouped and their detecting results are collected as whale to determine the channel quality. The channel quality is determined by interference collision ratio, which is the ratio of the number of interference events to the sum of the number of interference events and interference-free events. Interfered channels are disabled form the group. The Channel quality of each of plurality of channels is determined from detection results of each of plurality of groups so as to have a short assessment time and meanwhile a good frequency resolution may be retained.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: March 14, 2006
    Assignee: Mediatek Inc.
    Inventors: Hung-Kun Chen, Kwang-Cheng Chen
  • Patent number: 7010077
    Abstract: A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL1) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP1, to the second PLL (PLL2) to indirectly initially tune the second PLL. The bias voltage, CAP1, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP2, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: March 7, 2006
    Assignee: Agere Systems Inc.
    Inventors: Alfred Earl Dunlop, Wilhelm Carl Fischer
  • Patent number: 7010065
    Abstract: A method and apparatus are provided for word synchronization with large coding distance and fault tolerance for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). A Viterbi detector receives equalized PR4 samples including a predefined word synchronization pattern. The Viterbi detector is a dedicated detector optimized for detecting the predefined word synchronization pattern. The Viterbi detector includes a two-state Viterbi trellis and a word synchronization detector for the two-state Viterbi trellis. The predefined word synchronization pattern includes only even length magnets. The predefined word synchronization pattern is a repetition code including pairs of ones and pairs of zeros and includes multiple pattern match sequences. The Viterbi detector is optimized with branches removed from the Viterbi trellis, thus increasing coding distance.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: March 7, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Roy Daron Cideciyan, Jonathan Darrel Coker, Evangelos S. Eleftheriou, Richard Leo Galbraith, Todd Carter Truax
  • Patent number: 7003057
    Abstract: A reception AGC circuit includes a high-speed power calculating circuit for calculating the power of an input signal at a short period, a normal power calculating circuit for calculating the power at a normal period, a circuit for receiving a power calculation result from the high-speed power calculating circuit or normal power calculating circuit to calculate a feedback amplification value, and addition amplification value setting units for self-station communication and peripheral station monitoring which receive the feedback amplification value through a switch and add the feedback amplification value to an amplifier in use.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: February 21, 2006
    Assignee: NEC Corporation
    Inventor: Osamu Hasegawa
  • Patent number: 6999507
    Abstract: A method of determining cross channel interference in an Discrete Multitone (DMT) implementation of a Digital Subscriber Line (DSL) system. The cross channel interference is determined utilizing a residual impulse spectrum after implementation of a Time Equalization (TEQ) algorithm. In one application the cross channel interference value is used in a bit allocation algorithm to improve such that more bits are allocated to the channels with low interference and fewer bits are allocated to those channels having high interference. In this application the bit allocation algorithm is run twice, once before the interference measurement and once after.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: February 14, 2006
    Assignee: 1021 Technologies KK
    Inventor: Gary Qu Jin
  • Patent number: 6996166
    Abstract: An apparatus in a telecommunication system provides access to telecommunication services to subscribers at user terminals. Each terminal is separately connected to at least one access point via a xDSL modem and a communication network. The access point includes one or more xDSL modems with filters. As a result, a large number of subscribers can be connected in a short period of time, and the subscribers can consider the establishment of the connection as plug-and-play.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: February 7, 2006
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Sture Roos, Lars-Olof Haster
  • Patent number: 6996169
    Abstract: A decision feed back equalizer provides two feedback routines for one symbol-preceding decided data. The signal space is separated into decidable areas and uncertainty areas. Within each of decidable area the distance between any point and the signal point is small. Within each uncertainty area the distance between any point and the signal point is large. If the symbol-preceding equalized signal is in a decidable area, the piece of decided data is fed back, as it is presumed to be correct. If the symbol-preceding equalized signal exists in an uncertainty area, the piece of decided data is not fed back, as it is presumed to be in error. Here the one piece data is selected from all the predicted symbol-preceding decided data so that the instant equalized data is now in the decidable area. This piece of decided data is now fed back.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: February 7, 2006
    Assignee: Iwatsu Electric Co., Ltd.
    Inventors: Masaru Miyamoto, Koichi Ichimura, Atsushi Fujimoto
  • Patent number: 6993104
    Abstract: A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: January 31, 2006
    Assignee: ADTRAN, Inc.
    Inventors: Jason N. Morgan, Stacy M. Murphree
  • Patent number: 6983011
    Abstract: In a filter circuit of the present invention, a partial quantization value is computed by a quantization circuit according to a spread code and others in a unit at an arbitrary stage, where an integrating value is increased. The partial quantization value is successively added by an adder formed by a counter and is transmitted to a unit of the following stage. In an adder of the following stage, an analog residual is computed by subtracting an analog converted value of the partial quantization value, that is obtained by a D/A converter, from the integrating value so as to suppress an increase in the analog cumulative value. With this arrangement, the cumulative value is increased according to an increase in the number of taps, so that an analog adder can reduce power consumption, which is caused by expansion of a dynamic range at the following stage.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: January 3, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keita Hara, Kunihiko Iizuka
  • Patent number: 6980606
    Abstract: A branch metric calculation unit calculates a set of branch metric values for subsequent samples of the sampled input signal. Each of the set of branch metric values is an indication for the likelihood that an amplitude value of a sample corresponds to a particular state, a state being defined as a sequence of n-ary digits. A delay unit, which forms part of a delay chain of delay units, includes a first delay unit of the delay chain which is coupled to the branch metric calculation unit. A path metric calculation chain of path metric calculation units includes one or more path metric calculation units having first inputs coupled to a delay unit and second inputs coupled to a preceding path metric calculation unit. The path metric calculation unit calculates the path metric values from the branch metric values, a path metric value being on indication for the likelihood that a sequence of samples corresponds to a sequence of states.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: December 27, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Rob Otte, Willem Marie Julia Marcel Coene, Johannes Wilhelmus Maria Bergmans