Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Abstract: A feature extractor for a convolutional neural network (CNN) is disclosed, wherein the feature extractor is deployed on a member of the group consisting of (1) a reconfigurable logic device, (2) a graphics processing unit (GPU), and (3) a chip multi-processor (CMP). A processing pipeline can be implemented on the member, where the processing pipeline implements a plurality convolution layers for the CNN, wherein each of a plurality of the convolutional layers comprises (1) a convolution stage that convolves first data with second data if activated and (2) a sub-sampling stage that performs a member of the group consisting of (i) a max pooling operation, (ii) an averaging operation, and (iii) a sampling operation on data received thereby if activated. The processing pipeline can be controllable with respect to which of the convolution stages are activated/deactivated and which of the sub-sampling stages are activated/deactivated when processing streaming data through the processing pipeline.

Abstract: A memory management method, apparatus, and system are provided. The memory management method is performed by a memory management hardware accelerator, and the memory management hardware accelerator is coupled to an application subsystem and a communications subsystem. The application subsystem is configured to run a main operating system, and the communications subsystem is configured to run a communications operating system. The method includes: obtaining a set of memory addresses corresponding to dynamic memory space allocated by the main operating system to the communications subsystem, where the set of memory addresses includes one or more memory addresses; and sending some memory addresses in the set of memory addresses to a component of the communications subsystem.

Abstract: According to one embodiment, a method for remotely controlling peripheral devices in a mobile communication terminal includes acquiring a profile for a controlled peripheral device, configuring a control application for the controlled peripheral device based on the acquired profile, and controlling the controlled peripheral device using the configured control application.

Abstract: A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.

Abstract: An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained based on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.

Abstract: According to one embodiment, a system receives, at a host system a public attestation key (PK_ATT) or a signed PK_ATT from a data processing (DP) accelerator over a bus. The system verifies the PK_ATT using a public root key (PK_RK) associated with the DP accelerator. In response to successfully verifying the PK_ATT, the system transmits a kernel identifier (ID) to the DP accelerator to request attesting a kernel object stored in the DP accelerator. In response to the system receives a kernel digest or a signed kernel digest corresponding to the kernel object from the DP accelerator, verifying the kernel digest using the PK_ATT. The system sends the verification results to the DP accelerator for the DP accelerator to access the kernel object based on the verification results.

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transpose rectangular tiles. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first destination, second destination, first source, and second source matrices, the specified opcode to cause the processor to process each of the specified source and destination matrices as a rectangular matrix, decode circuitry to decode the fetched rectangular matrix transpose instruction, and execution circuitry to respond to the decoded rectangular matrix transpose instruction by transposing each row of elements of the specified first source matrix into a corresponding column of the specified first destination matrix and transposing each row of elements of the specified second source matrix into a corresponding column of the specified second destination matrix.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: An apparatus may include a serial data output port configured to send output data to a electronic device. The apparatus may include a serial data input port configured to receive input data from another electronic device. The apparatus may include a chip select output port configured to send output to the electronic devices connected in a daisy chain. The apparatus may include a interface circuit, configured to determine that a given electronic device is to selectively execute a first command. The interface circuit may be further configured to issue a complex command to the electronic devices connected. The complex command may indicate to the f electronic devices that additional commands are to be selectively executed.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Abstract: To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.

Abstract: A system, method, apparatus, and computer program product for exception handling between a robotic process automation system and a human operator where the exception is conveyed to the human via a messaging service. The exception is processed by a form algorithm which presents a graphical user interface via a dynamic web form that elicits human input of missing data elements. In cooperation with a validation algorithm, the dynamic web form ensures all missing data elements are provided by the human operator in the desired format. The dynamic web form allows a human to submit the requisite missing data elements, clear entered data elements, and mark the exception for offline processing.

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

Abstract: A method disclosed herein may include receiving a portal group from a node of a distributed storage system, the portal group comprising a plurality of network portals for accessing a storage unit, and transmitting data of the portal group to a first client and to a second client, wherein data transmitted to the first client and data transmitted to the second client each identify the plurality of network portals and indicate a different preferred network portal. The method may further include receiving a request from the first client to initiate a storage session that uses one of the plurality of network portals, establishing the storage session, wherein the storage session comprises multiple paths to the storage unit over at least two of the plurality of network portals, and providing data of the storage unit to the first client using the storage session.

Abstract: A method for generating and processing extended instructions and an apparatus using the method are provided. The method includes: transmitting, by a first device, a request packet according to an extended instruction that is generated based on a Gen-Z interface standard to a second device; and receiving, by the first device, a response packet including a result of performing the request packet from the second device. The extended instruction is generated based on a vendor-defined instruction set of the Gen-Z interface.

Abstract: A quantum message bus using superdense encoding to provide communications between services running on quantum computing devices and/or classical computing devices is disclosed herein. In one example, a message bus listener service executing on a first quantum computing device receives, via the message bus, a message sent from a sending service running on the first quantum computing device directed to a recipient service executing on a second quantum computing device. A quantum communication driver (QCD) service of the first quantum computing device identifies the second quantum computing device as a remote quantum computing device, and performs superdense encoding of the message using a first set of qubits that are entangled with a second set of qubits of the second quantum computing device. The first set of qubits are then sent to the second quantum computing device, which, in some examples, decodes and transmits the message to the recipient service.

Abstract: An optical line terminal (OLT) (1) includes an interface (I/F) board (2) configured to communicate with an external apparatus, a graphics processing unit (GPU) (4) configured to perform a first process, and a central processing unit (CPU) (3) configured to control the I/F board (2) and the GPU (4).