Abstract: A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

Abstract: A method for multiparty computation wherein a plurality of parties each compute a preset function without revealing inputs thereof to others, comprises: each of the parties performing a validation step to validate that computation of the function is carried out correctly, wherein the validation step includes: a first step that prepares a plurality of verified multiplication triples and feeds a multiplication triple to a second step when required; and the second step that consumes a randomly selected multiplication triple generated by the first step, wherein the first step performs shuffling of the generated multiplication triples, in at least one of shuffle in a sequence and shuffle of sequences.

Abstract: Methods and systems are provided for managing dynamic devices of an IHS (Information Handling System) that include re-programmable logic circuitry. The dynamic devices of the IHS are identified and the type of a dynamic device is determined based on operations implemented by the re-programmable logic circuitry of that dynamic device. The dynamic device is enrolled for management by a remote access controller of the IHS based on its determined type. Messages are registered for management of the dynamic device, where the messages are selected based on its determined type. Remote management of the dynamic device is initiated using the registered messages. Any programming that changes the type of the dynamic device of the dynamic device is detected. If a change is detected, the dynamic device is enrolled for remote management using updated messages based on its updated type.

Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described.

Abstract: Embodiments of the present disclosure provide an apparatus, comprising: one or more instruction executing circuitries, wherein each instruction executing circuitry of the one or more instruction executing circuitries is configured to execute an instruction of a corresponding instruction type, and an instruction scheduling circuitry that is communicatively coupled to the one or more instruction executing circuitries, the instruction scheduling circuitry is configured to: determine according to an instruction type of the instruction and a number of instructions that have been allocated to the one or more instruction executing circuitries, an instruction executing circuitry from the one or more instruction executing circuitries to schedule the instruction for execution, and allocated the instruction to the determined instruction executing circuitry.

Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.

Abstract: A complex programmable logic device includes a SGPIO analyzing circuit, a I2C analyzing circuit and a first multiplexer. The SGPIO analyzing circuit has a plurality of port analyzing circuits, a detecting circuit and a processing circuit. Each port analyzing circuit receives an input signal and outputs a first data. The detecting circuit detects the input signal of the first port analyzing circuit to output a detecting signal. The processing circuit captures port information of the first data outputted by at least part of the port analyzing circuits as a first control signal according to the detecting signal. The I2C analyzing circuit analyzes a data flow for outputting a second control signal according to an address command related to an address message, a control command and an input data. The first multiplexer selects the first control signal or the second control to be outputted according to a testing signal.

Abstract: Methods and systems for supporting similar thermal devices may involve collecting, by a thermal module on a management controller of an information handling system, device information about an add-in card, determining whether the add-in card was previously defined by matching the device against a table, searching the table based on the determination that the add-in card was not previously defined, determining whether the add-in card is supported by finding a match in the table, and applying a thermal tier associated with the match in the table based on the determination that the add-in card is supported. The device information collected may involve at least two of a reseller part number, description, device identifier, sub device identifier, vendor identifier, sub vendor identifier, slot identifier, lane width, and auxiliary power indicator. The search of the table may involve at least one of the description, lane width, and sub vendor identifier.

Abstract: A data processing method and apparatus, the method comprising: storing, at a first memory location in a memory, a first copy of a set of data; storing, at a second memory location in a memory, a second copy of a set of data; comparing the first copy to the second copy so as to identify, within the first copy, a pointer, the pointer being located at a first data element of the first copy, the pointer specifying a second data element of the first copy; determining an offset for the identified pointer, the offset specifying a number of data elements between the first data element and the second data element; and modifying the first copy such that the pointer within the first copy specifies the second data element using only the first data element and the offset.

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

Abstract: An electronic device and a control method thereof are disclosed. The electronic device includes: a memory storing input data, and a processor including a first register file and a second register file storing index data corresponding to kernel data, wherein the processor is configured to: based on a first command being input, obtain offset information of valid data included in a part of the index data stored in the first register file, based on the number of pieces of the offset information being greater than or equal to a predetermined number, store data packed with the offset information in a unit of the predetermined number in the second register file, and obtain output data by performing an operation regarding the input data based on the packed data.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

Abstract: An ALUA/aggregated switch latency reduction system includes a switch aggregation system coupling a server system including initiator devices to a storage system including target devices. The switch aggregation system includes a respective first switch device directly coupled to each of the target devices, and a respective second switch device directly coupled to each of the initiator devices. Each second switch device identifies an initiator device it is directly connected to, and transmits a respective first communication to each of the first switch devices that identifies that directly connected initiator device. When each second switch device receives a respective second communication from each of the first switch devices that identifies its directly connected target device, it identifies the first switch device directly connected to the target device that is in a session with its directly connected initiator device and, in response, causes packets to be forwarded to that first switch device.

Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for managing data transfer. A method for managing data transfer is provided, including: if determining that a request to transfer a data block between a memory and a persistent memory of a data storage system is received, obtaining a utilization rate of a central processing unit of the data storage system; and determining, from a first transfer technology and a second transfer technology and at least based on the utilization rate of the central processing unit, a target transfer technology for transferring a data block between the memory and the persistent memory, the first transfer technology transferring data through direct access to the memory, and the second transfer technology transferring data through the central processing unit. Therefore, the embodiments of the present disclosure can improve the data transfer performance of the storage system.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: store first execution information that includes first processing for a plurality of data and second processing executed subsequently to the first processing; convert the first execution information into second execution information by making a start timing of the second processing earlier than an end timing of the first processing, under a restriction of an execution order in which a data read in the second processing is executed after a data write in the first processing for each of the plurality of data, on the basis of an order of data writes included in the first processing and an order of data reads included in the second processing; and output the second execution information.

Abstract: Extending fused multiply-add instructions, the method comprising: receiving an extended fused multiply-add (FMA) instruction indicating one or more operands of a fused multiply-add (FMA) operation and one or more transformations to be applied to the one or more operands; and performing, based on the extended FMA instruction, the one or more transformations and the FMA operation.

Abstract: Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.

Abstract: Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.