Abstract: A stack management unit includes a stack cache to accelerate data retrieval from a stack and data storage into the stack. The stack management unit also includes an address pipeline to transfer multiple data words by a spill control unit and a fill control unit in the stack management unit. The address pipeline contains an incrementor/decrementor circuit, a first address register and a second address register. An address multiplexer drives either the output signal of the incrementor/decrementor or a cache bottom pointer to the first address register. The output terminals of the first address register are coupled to the input terminals of the second address register. A stack cache multiplexer drives either the address in the first address register or the address in the second address register to the stack cache. A memory multiplexer drives either the address in the address multiplexer or in the first address register to a slow memory unit.

Abstract: The present invention provides a method and architecture for allowing a device using a traditional one-time programmable technology to be programmed multiple times within the package. The present invention provides multiple programming without introducing the additional complexity of external pins or specialized packaging. An address counter and main array is provided using one-time programmable technology. The address counter selects a page in the main array to write the programmable information. The desired programming information is programmed into a first page while the additional pages remain unprogrammed. When additional information needs to be configured, the address counter is incremented and points to a new page in the main array where the new programming information may be stored. As a result, a number of programming configurations can be programmed into a one-time programmable technology.

Abstract: A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache.

Abstract: A FIFO storage circuit stores data transferred over a data bus in data groups having of one or more data units. The FIFO buffer includes a number of storage locations each configured to store a single unit of data. Each data groups on the data bus is accompanied by data-size information. A storage-location availability decoder receives the data-size information and allocates a number of consecutive storage locations in the FIFO storage circuit to allow for storage of the incoming data group. The FIFO then stores each unit of the data group, along with a data tag common to each unit, in consecutive storage locations. The next stored data group is then assigned a new data tag. The FIFO storage circuit reads from the storage locations in order of data tag. Checking consecutive storage locations for equivalent data tags enables the FIFO storage circuit to output the appropriate number of units for each data group.

Abstract: A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.

Abstract: A memory system having a dual port first in, first out (FIFO) memory which performs read operations in synchronism with a read clock signal and write operations in synchronism with a write clock signal. The read clock signal is asynchronous with respect to the write clock signal. A synchronizing engine is provided to synchronize a current write address with the read clock signal, thereby creating a synchronized write address. The synchronizing engine further synchronizes a current read address with the write clock signal, thereby creating a synchronized read address. The synchronized write address is compared to the current read address to determine if a FIFO empty condition exists. Similarly, the synchronized read address is compared to the current write address to determine if a FIFO full condition exists.

Abstract: A semiconductor storage device connectable to a host information processing apparatus having a flash memory section that stores data in sectors and wherein the flash memory section includes an address management table that stores information about the relation between logical sector numbers for data management in a host information processing apparatus and physical sector numbers for data management in the flash memory section. The flash memory section also includes a table state map that stores information about the physical locations at which the sector number information in the address management tables is stored. The semiconductor storage device also includes a flash memory control circuit for controlling data write and data read processing for the flash memory section.

Abstract: A method and system of providing a cache-coherency protocol for maintaining cache coherency within a multi-processor data-processing system is disclosed. In accordance with the method and system of the present invention, each processor has a cache hierarchy of at least a first-level cache and a second-level cache, and the first-level cache is upstream of the second-level cache. Each of the caches includes multiple cache lines, each associated to a state-bit field utilized for identifying at least six different states of the cache lines, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state. In response to an indication of a cache line containing a copy of information that was most recently accessed, the state of the cache line is transitioned from the Invalid state to the Recently-Read state.

Abstract: An on demand method of initializing a data storage medium, the method including the steps of: specifying a region of the data storage medium that is to be initialized in preparation for storing data in that region; setting up a table for keeping track of which portions of the region have been initialized; in response to receiving a request for accessing a specified location within the region, checking the table to determine whether the location to which access is being requested had been previously initialized; if the table indicates that the specified location has not been previously initialized, initializing that specified location within the data storage medium; and updating the table to indicate that the specified location within the data storage medium has been initialized.

Abstract: A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

Abstract: A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

Abstract: An information recording medium is reproduced by an information reproducing apparatus for controlling a reproduction of record information based on a search control information recorded together with the record information, The medium includes: processed record information including a plurality of information units generated by applying a signal processing onto the record information; a search control information for searching, out of the processed record information, a reproduction record unit which is a record unit including the record information to be reproduced. The search control information is multiplexed with the processed record information. The reproduction record unit includes an initial one of the processed record information constituting the information units included in the reproduction record unit which is recorded at a recording position on a recording medium corresponding to a head portion of an area where the processed record information in the reproduction record unit is recorded.

Abstract: A recording apparatus generates a plurality of pieces of data to be recorded on a storage medium, and to be reproduced in a plurality of modes of reproduction; generates identification information indicating a reproduction mode; and writes the pieces of data and the identification information in the storage medium so that the pieces of data are written in a sequential order in which to be reproduced. The sequential order is independent of the plurality of reproduction modes. Each piece of data is accompanied by the identification information for that piece of data. A reproducing apparatus reads the pieces of data and the identification information, in the sequential order; detects the identification information which accompanies the respective pieces of data; and reproduces the pieces of data in the corresponding ones of the plurality of reproduction modes based on the accompanying identification information.

Abstract: Flash memory circuits provide sector protection or file protection with protection attribute status bits held in a flash memory array. The sector protection protects memory data based on the physical location of the data. The flash memory array is divided into a number of memory sectors. Each memory sector can be protected independently. The size of the memory sector is flexible and may be as large as the whole memory array or as small as a single bit group. Each memory sector has protection bits stored in a protection bit array for indicating the protection state of the sector. A parallel protection structure providing both sector protection and block protection is also included. The parallel protection allows small size data protection as well as large size block protection. File protection protects memory data on a file basis regardless of the physical location of the data. Each file has protection bits stored in an attribute memory for indicating the protection state of the file.

Abstract: A method and system of collaboratively caching information to allow improved caching decisions by a lower level or sibling node. In a caching hierarchy, the client and/or servers may factor in the caching status at the higher level in deciding whether to cache an object and which objects are to be replaced. The PICS protocol may be used to pass the caching information of some or all the upper hierarchy down the hierarchy. Furthermore, the caching status information can also be used to direct the object request to the closest higher level proxy which has potentially cached the object, instead of blindly requesting it from the next immediate higher level proxy. A selection policy used to select objects for replacement in the cache may be prioritized not only on the size and the frequency of access of the object, but also on the access time required to get the object if it is not cached.

Abstract: A method and system for speculatively sourcing data among cache memories within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then sourced from a secondary cache memory within the second processing unit onto a system data bus concurrently with invalidating a copy of the requested data from a primary cache within the second processing unit. During this time, the second processing unit is also pending for a combined response to return from all the processing units.

Abstract: The write notification during copy system functions to enable the data processor to manage the data file copy function of a disk data storage subsystem in a manner that minimizes the expenditure of data processor resources. This is accomplished by the write notification during copy system determining the source volume on the data storage subsystem, the target volume on the data storage subsystem and identifying the extents of both. The write notification during copy system then transmits data to the data storage subsystem, representative of the assignment of DASD full tracks from the source location on the data storage subsystem as well as DASD full tracks from the target location on the data storage subsystem. The data processor based write notification during copy system then uses ECAM channel programs to instruct the data storage subsystem to perform the data file copy operation using snapshot track pointer copy operations.

Abstract: In a virtually addressed and physically indexed cache memory, the allocation of a color of a cache entry can be changed for a color allocation of the virtual and physical pages by assigning a color information to each cache entry, by which a second cache address operation is executed after an unsuccessful first cache address operation. Should there still be no cache hit, another cache addressing is attempted by means of a color correction, i.e. an indexing of the cache memory using, among others, the physical color. Should this cache address operation also fail to produce a cache hit, there is a cache miss.

Abstract: Replacing a human operator, an automated message processing system communicates with a data storage subsystem that includes a tape library and a storage controller. The automated message processing system receives messages from a data storage subsystem concerning the availability of tape drives in the tape library. Such messages are selectively routed to one of many specialized expert local facilities (ELFs) for performance of a designated function, such as generation of an appropriate output messages. The ELFs receive input messages and transmit output to the data storage subsystem in order to oversee allocation and use of data storage drives in the data storage subsystem.

Abstract: In a processor employing separate instruction and data caches in at least one cache hierarchy level, a cache control instruction forces modified data within the separate data cache to a lower cache hierarchy level. An existing cache access attribute is employed to distinguish between occasions when the data must be written all the way to main memory and occasions when the data need only be written to a cache hierarchy level from which fetches are made to the separate instruction cache. Thus, the separate instruction and data caches may be made coherent without writing all the way to main memory, but the ability to write modified data to main memory whenever necessary is preserved. Utilization of the existing attribute avoids increasing processor complexity and/or resources.