Abstract: A method and apparatus for controlling the access of multiple processors to a shared memory device in a computer or other processor-based system. An exemplary embodiment includes an embedded processor and a host processor, both of which share access to a single-port random access memory (RAM). An access control circuit is provided which includes a control register with a first storage element corresponding to the embedded processor and a second storage element corresponding to the host processor. The access control circuit utilizes access request bits stored in the first and second storage elements to generate a select signal which is applied to the select signal inputs of a group of multiplexers. The multiplexers select either the embedded processor or host processor control, address and data signal lines for connection to the single-port RAM.

Abstract: A computer system refreshes dynamic memory in a burst, but allows other memory access requests to preempt a burst refresh before the burst completes. In another aspect, once a burst refresh begins, it is allowed to continue for a number of refresh cycles which is greater than the number of refresh cycles then due; that is, until a time when the number of refresh cycles due is negative. This technique, referred to herein as "refresh-ahead", effectively helps to shift memory refresh activity into periods of bus time which would otherwise be idle.

Abstract: A digital data storage subsystem comprises a cache memory, a digital data store and a host adapter. The cache memory includes a plurality of cache slots, each of which caches digital data from the digital data store for access by the host adapter. The digital data store includes a disk drive, in which data is stored in the form of variable- or fixed-length records. The storage controller identifies one of said data storage sections as constituting a current owner of respective ones of the cache slot, and is responsive to record staging requests to selectively transfer records from the data storage section identified as the owner of said at least one cache slot to said cache slot for caching. In staging records for the current owner, the storage controller may, but need not, over-write records that were previously staged in the cache slot for previous owners.

Abstract: A memory in a computer system includes a visible portion and a hidden portion. The visible portion of the memory is addressable by a processor and the operating system operating within the computer system. Addressability by either the processor or the operating system is excluded to the hidden portion of the memory. The hidden portion of the memory is used for storing data transmitted by either the processor or the operating system. A communications area, located in the visible portion of memory receives requests for data access from either the processor or the operating system. A hidden server which addresses both the visible portion of memory and the hidden portion of memory receives requests for data access from the communications area and initiates data access from the hidden memory.

Abstract: A circuit for selecting a base memory to be accessed by a microcontroller in response to a command from the microcontroller. An input receives the command from the microcontroller. The command selectively instructs the circuit to reset the microcontroller and signal the microcontroller to access an internal memory as the base memory. Also, the command selectively instructs the circuit to reset the microcontroller and signal the microcontroller to access an external memory as the base memory. A reset output is used to send the reset signal to the microcontroller, and a memory select output is used to send a memory select signal to the microcontroller.

Abstract: A circuit and method is provided for implementing a content addressable memory circuit (100) in which at least one output word is produced which corresponds to the content of a match word. A binary search logic circuit (103) binarily searches the memory array (101) to find a match entry with multiple words whose content is equal to that of an input value with multiple words. The amount of words in each match entry is user programmable and defined at startup. The CAM (100) is capable of masking out words to be compared or outputted and allows overlapping of words to be compared and outputted. Output signals indicate whether a match has been found.

Abstract: A memory 601 comprising a plurality of static random access cell arrays 701, and a plurality of sets of latches 703 each for storing address bits associated with data stored in a corresponding one of the static random access cell arrays 701. Bit comparison circuitry 503 compares a received address bit with an address bit stored in each of the plurality of sets of latches 703 and enables access to a selected one of the static random cell arrays 701 corresponding to the set of latches 703 storing an address bit matching the received bit.

Abstract: A method and apparatus for configuring a mass storage system, in which an array of disk storage devices connect to a storage controller and a plurality of host computers also connect to the storage controller, provide the capability, using a convenient graphical user interface at the host computer, for enabling the user at the host computer to determine the status and configuration of the system. The user can also, using the graphical user interface, modify the system status or configuration. Various graphical user interface techniques can be used including "click and drag" and other user friendly presentations and operations. The system uses either proprietary communications channels between disk drive controller and host computer, or modifies standard protocols in order to enable the necessary communications to occur.

Abstract: A system and related architecture for providing random access cache storage between a processor accessing data at high speed and in small block units and a mass storage medium holding data in large transfer units. Lossless data compression is applied to large transfer units of data before storage in a DRAM. Cache address space is assigned in allocation units which are assigned without a prespecified pattern within the DRAM but linked through chains. The chain lengths are adjusted to match the compressibility characteristics of transfer units and include resources for scavenging residuals. Logical blocks materially smaller than the transfer units are accessed and decompressed during readout from the DRAM. The system architecture provides resources for accessing the individual logical blocks through an index. The invention is particularly suited for a disk drive cache system having a small cache DRAM in conjunction with a magnetic or optical disk mass storage system reading highly compressible data.

Abstract: A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.

Abstract: A highly integrated central processing unit employs a single external physical bus having first and second protocols to support an L2 cache and a general purpose peripheral interface respectively, to avoid bond-out of the CPU bus to the external world and to steal unused bandwidth for L2 cache accesses while maintaining a standard peripheral bus interface.

Abstract: A packet-data FIFO buffer system comprises a FIFO buffer with a series of FIFO memory locations. Each FIFO memory location includes a data section for storing a packet data word and a flag section for storing an indication of whether or not the associated data section includes the last word of a packet. The FIFO buffer capacity is not limited to the number of maximum length packets it can hold; instead, a greater number of small packets can be stored. This increases the effectiveness of available FIFO memory and minimizes communication delays along the channels serviced by the FIFO. The FIFO design is simple and fairly self contained so that minimal external logic and control is required. In addition, an indication of the presence or absence of a complete data packet in the FIFO buffer can be easily obtained by logically adding (ORing) the contents of the flag sections.

Abstract: A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic.

Abstract: An expandable-set, tag, cache circuit for use with a data cache memory comprises a tag memory divided into a first set and a second set for storing, under a single address location, first and second tag fields representative of first and second data, respectively. The tag memory also stores first and second signals representative of which of the sets is the least recently used. A comparator is responsive to a tag field of an address representative of requested data as well as to a first tag field output from the tag memory for producing an output signal indicative of a match therebetween. A second comparator is responsive to the same tag field of the address and to a second tag field output from the tag memory for producing an output signal indicative of a match therebetween. A first logic gate is responsive to the first and second comparators for producing an output signal indicative of the availability of the requested data in the data cache memory.

Abstract: A memory 400 comprises a plurality of banks 401 and global access control circuitry 406. Each of the plurality of banks includes first and second arrays 506, 402 of memory cells, first accessing circuitry 413, 507 for selectively accessing cells in the first array in response to address bits, and second accessing circuitry 404, 413 for selectively accessing cells in the second array in response to address bits. Storage circuitry 502 within each bank 401 stores previously received address bits. Circuitry for comparing 503 within each bank compares received address bits with stored address bits in storage circuitry 503, with first accessing circuitry 413, 507 accessing cells in first array 506 addressed by the stored address bits when stored address bits and received address bits match and second accessing circuitry 404, 413 accessing cells in second array 402 addressed by the received address bits when the stored address bits and the received address bits differ.

Abstract: A system and method for maintaining logically consistent backups using minimal data transfer are presented. A system comprises a backup system having a backup storage device and one or more primary systems having mass storage devices that are to be backed up on the backup storage device. The primary systems identify changes that are going to be made to the mass storage device. The combined effected locations in the mass storage device of these identified changes are then captured in a static snapshot when the mass storage device is in a logically consistent state. Only those data blocks changed since the last backup are then transferred to backup system. The backup system can then store these changes or apply the changes to the backup storage device in order to bring the backup storage device current to a particular point in time.

Abstract: A cache is provided which prefetches data words associated with a particular addressing mode. When a data word is accessed in response to the execution of an instruction, the data word is discarded by the cache. Data which is accessed in a use-once fashion (such as DSP data, for example) may be thereby available with cache-hit memory access times instead of main memory access times. The present cache prefetches data words spaced at regular or irregular intervals, wherein the interval is specified by the addressing mode of the instruction. Multiple words within a data stream may be successfully prefetched. The cache described herein may be incorporated into a microprocessor having a conventional cache as well. Data which is indicated to be used once may be stored in the present cache, while data exhibiting locality may be stored in the conventional cache. Data which exhibits locality is thereby retained within the cache system when use-once data is accessed.

Abstract: A microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to the contents of a second cache memory in a second mode of operation. The mode of operation is set by control logic. The mode is selected by setting a bit in a mode control register. When the bit is set, the control logic changes the system from a first mode in which the second memory serves as additional on-chip cache memory to a second mode in which the second memory stores tags for an external level 2 cache memory. The invention provides a flexible cache structure in which increased on-chip cache is provided or tag memory area is provided for an off-chip level 2 cache.

Abstract: A guest execution control system method and computer process for a virtual machine system having a main storage for holding a state descriptor of a guest virtual machine, and a plurality of instruction processors each starting execution of the guest virtual machine by executing an execution start instruction for the guest virtual machine. Execution instruction information in the state descriptor indicating whether execution of the guest virtual machine is to be finished is changed when a state of the virtual machine satisfies a predetermined condition during execution of the guest virtual machine. The execution instruction information is held at an address in the main storage.

Abstract: A microprocessor is provided with an output pad logic circuit for each of its output lines. Each output pad logic circuit advantageously includes first and second latch circuits each configured to store output information at the same time. When the processor detects that a snoop write-back is pending, the second latch, referred to as a restore latch, preserves the information contained therein. During the snoop write-back operation, only the first latch stores the snoop write-back information and conveys the information to the output pins. When the snoop write-back operation is complete, an output enable signal is provided to the second latch to cause its stored information to be conveyed to the output pins upon the beginning of the next bus cycle. Subsequently, the second latch resumes capturing information along with the first latch.