Abstract: A data processing system for transferring data is provided. This system includes central processing units (CPUs 20, 22, 24 and 26) and storage units (30 and 32 with 100-105 and 110-115) which are interconnected by a network (10). The CPUs (20, 22, 24 and 26) include a request process (133) and a storage process (130). The storage process (130) controls access to the storage unit (30 with 100-105 and 110-115). Software routines (220) are used to provide direct access to the storage unit (30 with 100-105 and 110-115) by the request CPU (22). The request CPU (20) is the CPU containing the request process (133). A virtual memory address for a buffer (160) of the request CPU (22) is created in the request CPU (22). The virtual memory address along with a storage unit access request are sent to the CPU (20) containing the storage process (130). A work request including the virtual memory address to sent from the storage process (130) to the storage unit (30 with 100-105 and 110-115).

Abstract: A method and apparatus for facilitating the streaming of data over a system bus between a memory and a DMA device. This is accomplished by doing a speculative cache look-up, or snoop, on a next cache line during or immediately following the access of a current cache line. This is done for DMA transfers when the first DMA address is received, and before subsequent addresses are received. Thus, a determination of whether the cache line is in the cache can be done in advance, allowing the next cache line of data to stream over the bus to or from the cache without waiting for the next address from the system bus or requiring a rearbitration for the system bus.

Abstract: A data processing system dynamically balances allocation of storage areas in a shared coupling facility that is devoted to storage of directory entries and data blocks. Each directory entry includes information regarding the validity of a data block that is locally stored by one or more processor modules in the data processing system. The system includes a coupling facility having a cache memory wherein a first portion is allocated to storage of data blocks and a second portion is allocated to storage of directory entries. Each directory entry, associated with a data block, indicates the validity or invalidity of data contained in a copy of the data block maintained by a connected computer module in its local memory. Each computer module, upon requiring a first data block and determining that (i) the first data block is present in its local memory (i.e., a buffer "hit"), but (ii) is not marked valid and (iii) is not present in the coupling facility (i.e.

Abstract: Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache.

Abstract: A memory controller has an address counter, a control circuit, and registers for receiving and storing a starting address, a block fetch size value, and write data. The address counter counts from the starting address, thereby generating successive addresses from which data in a memory device are read. When the amount of data designated by the block fetch size value has been read, the control circuit reloads the starting address into the address counter, the address counter generates the same successive addresses again, and the write data are written at these addresses. A block read-and-clear or block read-and-replace operation is thereby carried out. The memory controller may also have registers for storing the read data, and a logic operation circuit for combining the read and write data to carry out a block read-modify-write operation.

Abstract: An instruction translation look-aside buffer (iTLB) for attaining very high data processing throughput comprises a 2.sup.n -way set associative data array having m sets, where m and n are both integers greater than or equal to one, with associated data and tag arrays. A set address selects one of the m sets for reading, resulting in a readout of all 2.sup.n ways of the tag, valid and data arrays. Comparison logic determines if a match exists between the 2.sup.n tags read out from the tag array with a portion of the linear address. A "hit" to a certain way causes a hit line signal to select data for the corresponding way, which is output from a 2.sup.n :1 static multiplexer and contains the physical address translation. Each of the hit lines are precharged during a first phase of a clock cycle. The comparison logic operating during a second phase of a clock cycle. Thus, the matching is accomplished in a single clock cycle.

Abstract: An improved cache coherency protocol is set forth that assures that a collection of processors in a multi-cache system configuration do not disagree about the precedence ordering of store operations that can originate from any and all processors within the system. The protocol maintains coherency while allowing lines to be modified by one processor while other processors access a prior unmodified copy of the line. The benefit of such a system is that line modification need not be done only for lines that are exclusive within the cache that is associated with the modifying processor. The manner in which this coherency is achieved is through the use of line status register which maintains the status of every line in the system and a processor modification register which maintains the identity of all processors that have been granted permission to modify a line that is shared with other processors.

Abstract: A method and apparatus for creating a new partition in a hard disk drive of a computer system and installing software (e.g., system software) into the new partition. The method of the disclosed invention reads a diskette for a unique diskette signature which, if present, indicates that the diskette contains software to be installed in a new partition. If the unique diskette signature is found to be present on a diskette, then a new partition is created on the computer system's hard disk drive. The new partition can be of any size, and the size can, for example, be either fixed based upon predetermined settings or user-selected. After the new partition is created, it is assigned to logical drive 80h, the DOS boot drive. Once assigned to logical drive 80h, the invention boots to the diskette and the partition installation software contained on the diskette is executed. The installation software contained on the diskette then installs the software into the new partition.

Abstract: A system for indicating byte-order format information of multi-byte data contained in a cache memory. A plurality of cache lines resident in the cache memory each include cache line data copied from a main memory block, and a corresponding cache line tag. Each cache line tag includes a main memory address mapping field for providing main memory address mapping information of the cache line data of its associated cache line and a cache line byte-order format field for indicating a byte-order format of the cache line data of its associated cache line. The invention also includes a cache management system and method for managing cache move-in operations in a computer system compatible with multiple byte-order formats having a main memory organized in a default byte-order format and a cache memory.

Abstract: When cache misses occur simultaneously on two or more ports of a multi-port cache, different replacement sets are selected for different ports. The replacements are performed simultaneously through different write ports. In some embodiments, every set has its own write ports. The tag memory of every set has its own write port. In addition, the tag memory of every set has several read ports, one read port for every port of the cache. For every cache entry, a tree data structure is provided to implement a tree replacement policy (for example, a tree LRU replacement policy). If only one cache miss occurred, the search for the replacement set is started from the root of the tree. If multiple cache misses occurred simultaneously, the search starts at a tree level that has at least as many nodes as the number of cache misses. For each cache miss, a separate node is selected at that tree level, and the search for the respective replacement set starts at the selected node.

Abstract: The system of the preferred embodiment of the invention contains a processor as well as a permanently mounted programmable FLASH memory in which the firmware resides. The system makes use of a socket in which a memory device can be installed. The socket accepts a firmware update memory device which has stored thereon the firmware revisions or replacement firmware. Once the firmware update memory device is installed, the processor downloads the instructions contained therein to the permanent FLASH memory device. Once the program is transferred to the permanent memory, the system operation is not dependent on the reliability of the socket. In addition, program changes can be input to the system without requiring that the system be equipped with a data input/output device, such as a modem, floppy disk drive or the like.

Abstract: The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.

Abstract: Control operations to access a memory changes respective priorities of the operations depending on the situation of the memory, and the operations are arbitrated and scheduled according to the respective, changed priorities, in order to avoid concentration on or rejection of a specific memory access operations and to eliminate an ineffective period. This realizes an efficient memory system without increasing the capacity of a buffer memory, the width of a memory bus, or an operating frequency.