Abstract: A standard thick silicon charge-coupled device (FIG. 1A) has its pixel face mounted to a transparent, optically flat glass substrate using a thin layer of thermoset epoxy. The backside silicon of the charge-coupled device is thinned to 10 .+-.0.5 um using a two-step chemi-mechanical process. The bulk silicon is thinned to 75 um with a 700 micro-grit aluminium oxide abrasive and is then thinned and polished to 10 um using 80 nm grit colloidal silica. Access from the backside to the aluminum bonding pads (36 of FIG. 5) of the device is achieved by photolithographic patterning and reactive ion etching of the silicon above the bonding pads. The charge-coupled device is then packaged and wire-bonded in a structure which offers support for the silicon membrane and allows for unobstructed backside illumination.

Abstract: A method of producing a buried insulation layer used to channel current through a small opening through the insulation layer. Ions are implanted to a depth controlled by the ion kinetic energy and are activated to form the insulation layer. A groove, preferably V-shaped is formed to produce through the insulation layer in opening through which current is to be channeled. Epitaxial layers are formed on the grooved surface to produce an integrated circuit that channels current through this opening.

Abstract: There is provided a method for producing a semiconductor device having a semiconductor layer in which carbon is implanted as an impurity. The method includes the steps of: implanting fluorocarbon ions in a semiconductor layer; and annealing the semiconductor layer to activate the implanted ions.

Abstract: A method for forming a mask pattern for contact hole in a highly integrated semiconductor device is disclosed. The method according to the invention utilizes a SOG film in order to form an accurate and compact mask pattern for the formation of a contact hole within the highly limited area at a predetermined semiconductor layer where a sizable step difference exists. The method according to the invention is also applicable for manufacturing a multi-layered highly integrated semiconductor device.

Abstract: A method for fabricating an all silicon absolute pressure sensor employing silicon-on-insulator structures. More particularly, a method for fabricating an all silicon absolute pressure sensor based upon an ungated metal-oxide semiconductor field-effect transistor which offers a high degree of immunity to temperature effects, increased reliability, minimal substrate parasitics, reduced manufacturing variations from device to device, as well as inexpensive and simple fabrication.

Abstract: The invention relates to a process for pickling stainless steel products, in which a pickling bath is used having the initial composition:HF 10 to 50 g/lDissolved ferric iron (Fe.sup.3+).gtoreq.15 g/lWater: as requiredat a temperature of between 15.degree. and 70.degree. C., characterized in that, during the pickling operation(s), the ferric iron content of the bath is maintained at at least 15 g/l by oxidation of the bath comprising at least one or several injections of air in a total quantity greater than or equal to 1 Nm.sup.3 per m.sup.2 of pickled stainless steel and per hour of pickling of each unit of surface area pickled.The process of the invention applies particularly to the industrial pickling of stainless steel sheets and strips, in which it is possible to avoid the use of nitric acid and the resulting pollution.

Abstract: A semiconductor memory device includes a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in a substrate and arranged in a matrix manner, a MOS capacitor and a MOSFET formed on side surfaces at lower and upper portions, respectively, of each pillar projection, a diffusion layer of a source or drain of each MOSFET formed in an upper end face of the pillar projection, and a bit line connected to the diffusion layer. The bit line is in contact with the upper end face of the pillar projection in a self-alignment manner.

Abstract: A method of manufacturing a photovoltaic device, wherein an amorphous semiconductor layer of one conductivity type doped with impurities which determine the conductivity type is formed on a substrate having a conductive surface, an insulating film is formed on this amorphous semiconductor layer, the insulating film is patterned to partially form aperture regions where the surface of said amorphous semiconductor layer is exposed, an intrinsic amorphous semiconductor layer on said insulating film and the aperture regions formed over the substrate, the amorphous semiconductor layer of one conductivity type and the intrinsic amorphous semiconductor layer are thermally treated, crystallization is advanced using the amorphous semiconductor layer of one conductivity type located beneath said aperture region as a core to form a polycrystal semiconductor layer of one conductivity type, a semiconductor layer of the other conductivity type is formed on this polycrystal semiconductor layer, and an electrode is formed in

Abstract: A process of forming field oxide regions using a field oxidation performed in a dry oxidation environment in a temperature equal to or greater than approximately 1000.degree. C. The dry oxidation reduces or eliminates the formation of Kooi ribbons, and the high temperature field oxidation allows the field oxide to flow, thereby reducing physical stresses normally associated with field oxidation performed at temperatures below 1000.degree. C. The high temperature field oxidation also greatly reduces the ratio of the length of the bird's beaks formed during the field oxidation to the thickness of the field oxide, allowing smaller active regions to be formed. The thinner field oxide regions, in turn, make it possible to perform the field implant after the field oxidation, thereby avoiding the lateral encroachment problem and controlling source to drain or drain to source punch-through under the gate.

Abstract: A self-aligning ion-implantation method for forming multi-gate MOS transistor structures within a semiconductor cell array on a substrate is provided. Each structure includes a plurality of first gate electrode layers and a plurality of second gate electrode layers arranged in an alternating sequence over a channel region between a drain and a source region and insulated from each other.

Abstract: A silicon layer having an increased surface area by providing a highly granulated surface area, and a method for manufacturing the same are disclosed. The highly granulated surface of the silicon layer of the present invention provides greater surface area relative to the surface area of the present silicon layer where both layers have the same (length and width) dimensions. The present invention provides a silicon layer for a charge storage electrode having an increased surface area by forming the surface of the silicon layer into a highly granulated topography, which is used as a charge storage electrode, to enable the capacitance of the stacked capacitor to be increased relative to a prior art stacked capacitor having the same area of the silicon layer but with less granulated topography, and provides a process of making a highly granulated silicon layer having an increased surface area relative to the existing methods of making a silicon layer and its associated surface area.

Abstract: A semiconductor wafer is provided with magnetic material about the periphery for magnetically clamping the wafer on a seating gasket at the processing station. The seating gasket is annular for peripherally supporting the wafer. An electro-magnet establishes a peripheral station magnetic field which attracts the wafer magnetic material to form the clamp. The station magnetic field may by reversed to levitate the wafer onto and off of the seating gasket.

Abstract: This is a method of forming a semiconductor-on-insulator wafer with a single-crystal semiconductor substrate.

Abstract: An isolation method of semiconductor devices comprises the steps of forming a multilayer, defining both active and isolating regions, forming a channel stopper, removing the multilayer on a nitride layer to form a capping oxide layer, removing the multilayer on the nitride layer and a polysilicon layer to form an isolation layer, forming spacers at sidewalls of the isolation region, forming a gate oxide layer and a gate oxide electrode, and forming a second conductive diffusion regions, wherein the CVD process and photolithography methods are applied in formation of the isolating layer not to result in the bird's beak and dislocation caused by stress and the channel stopper is formed by ion-implantation of impurity without its diffusion not to contact with the isolating layer by the spacers on the sidewalls thereof in its diffusion region which is formed by the ion-implantation.

Abstract: A method is now utilized for stripping costly electrocatalytic coatings from valve metal substrates while maintaining excellent integrity of the substrate metal. The removed metal may also be conveniently recovered. A molten salt bath of alkali metal hydroxide and alkali metal salt of an oxidizing agent is employed. Careful electrode to bath contact times and bath temperatures are observed. Additionally, a dilute mineral acid rinse and water rinse, with scrubbing in one of the rinses follows such molten salt bath contact for the electrode. Solids recovered from the rinses are combined.

Abstract: An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:(a) forming on a silicon substrate a silicon nitride layer having a predetermined pattern and a tapered-slant side wall, between the silicon nitride layer and the silicon substrate being formed a silicon oxide layer,(b) subjecting the silicon substrate to an isotropic etching using the silicon nitride layer as a mask to form a recess on the substrate, the recess extending to and under the side wall of the silicon nitride layer, and(c) forming a channel stopper region by implanting an impurity into the silicon substrate through the recess-formed surface, and thereafter growing and forming a LOCOS layer on the recess-formed surface to obtain an isolation region.

Abstract: An isolation method for a semiconductor device, and comprises the steps of: sequentially forming a first silicon nitride film, an oxide film, and a second silicon nitride film on a substrate and forming an opening to define an isolation region between devices; forming a spacer at the edges of the opening and implanting impurities in the substrate; removing the exposed part of the first silicon nitride film, and then removing the spacer; growing a field oxide film, and sequentially removing the second silicon nitride film, the oxide film, and the first silicon nitride film. In a second embodiment, the first silicon nitride film and part of the substrate are removed, and then the spacer is removed during the process of removing the exposed part of the first silicon nitride film and the spacer. Accordingly, the depth to which the field oxide film is buried is controlled by the etching depth of the substrate, thereby increasing the effective isolation distance.

Abstract: A method of producing a GaAs single crystal substrate comprises the steps of conducting a first-stage annealing by vacuum-sealing a GaAs single crystal wafer and arsenic in a heat-resistant vessel and heating the wafer to a temperature of 1050.degree. to 1150.degree. C. while exposing it to arsenic vapor pressure, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing the wafer from the vessel, etching the wafer and placing it in another vessel, conducting a second-stage annealing by heating the wafer to a temperature of 910.degree. to 1050.degree. C. in a non-oxidizing atmosphere, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing it from the vessel, etching the wafer, conducting a third-stage annealing by vacuum-sealing the wafer and arsenic in the heat-resistant vessel and heating the wafer to a temperature of 520.degree.-730.degree. C. while exposing it to arsenic vapor, and cooling the wafer at least down to 400.

Abstract: A process for the formation of material layers such as amorphous silicon is disclosed. When a precursor gas such as silane is utilized to form amorphous silicon, silicon crystals are often formed on top of the amorphous silicon layer. The crystals are created by the presence of low pressure silane in the reactor at the end of the deposition cycle. Formation of crystals is inhibited by lowering the temperature before silane flow is terminated.

Abstract: A method is provided for forming isoplanar isolated regions in an integrated circuit, and an integrated circuit formed according to the same. According to a first disclosed embodiment, a first epitaxial layer is formed over a substrate, the substrate having a (100) crystal orientation. A first masking layer is formed over the first epitaxial layer. The first masking layer is patterned and the first epitaxial layer is etched to form openings. The sidewalls of these openings have a (111) crystal orientation. The first masking layer is then removed and a second masking layer is formed in the openings. The first epitaxial layer is anodized and oxidized. The second masking layer is removed and a second epitaxial layer is formed in the openings. According to an alternate embodiment, after the first epitaxial layer is anodized, the second epitaxial layer is formed in the openings and the first epitaxial layer is then oxidized.