Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor, sensing transistor having a floating gate, control gate with a capacitive coupling to the floating gate and a tunnel area with thin oxide, comprises a first step involving the definition of active areas free of field oxide, a second step involving an ionic implantation at a coupling area between the control gate and the floating gate, a third step involving the creation of gate oxide at the active areas, a fourth step involving an additional ionic implantation at said coupling area between the control gate and the floating gate and at said tunnel area, a fifth step involving the removal of the gate oxide superimposed over said areas, a sixth step involving the differentiated growth of coupling oxide and tunnel oxide at said coupling areas and tunnel areas and a seventh step involving the deposition of a layer of polysilicon constituting the floating gate.

Abstract: A conductivity modulation type semiconductor device comprises a semiconductor anode substrate of a P type having two surfaces, a semiconductor substrate of an N type having two surfaces, the semiconductor substrate having a high impurity layer-like region on one surface thereof and a low concentration drain region on the other surface thereof, a body region of P type formed in the drain region and exposed at one surface of the semiconductor substrate, source regions of an N type formed in the body region and exposed at the other surface of the semiconductor substrate, and a gate layer formed within the isulating layer, which extends between the source and drain regions, on the body region. The other surface of the anode substrate is polished and is intimately joined to the polished surface of the semiconductor substrate to form a junction layer therebetween.

Abstract: Process for the manufacture of lubricating base oils wherein a hydrocarbon feedstock is catalytically treated in the presence of hydrogen at elevated temperature and pressure and wherein at least part of a heavy fraction of the material obtained is subjected to dewaxing, in which process a hydrocarbon feedstock is used containing flashed distillate produced via a residue conversion process.

Abstract: Methods for reducing encroachment of the field oxide into the active area on a silicon integrated circuit are disclosed. The present invention modifies the conventional LOCOS technique for forming active areas and field oxide areas on a silicon substrate. Rather than fully forming the field oxide regions immediately after the silicon nitride layer is patterned and etched on the substrate, a thin field oxide is grown. This oxide is partially wet etched to leave a ribbon of bare silicon around and extending under the edges of the silicon nitride mask. An additional nitride layer is deposited over the entire wafer and anisotropically etched to form a nitride spacer between the original nitride mask and the partially grown field oxide. The nitride spacer seals the edge of the active area by inhibiting the diffusion of oxygen under the nitride mask. During subsequent field oxidation, the nitride spacer greatly reduces the encroachment of the field oxide into the active area.

Abstract: A process for manufacturing a trench isolation device is mainly comprised of steps of forming a trench in an impurity ion doped region in a semiconductor substrate after the impurity ion doped region has been formed by ion implantation. The ion energy for the ion implantation is charged from a low energy level to a high energy level, or vice versa, in order to provide a uniform vertical doping profile or a graded vertical doping profile. By this method, field dope layers completely surround the trench in the trench isolation device.

Abstract: A method is provided for producing trench structures having vertical, smooth side walls and straight, flat trench floors in silicon substrates. The reactive ion etching is implemented in a triode single-wafer plate reactor upon use of an etching mask preferably composed of SiO.sub.2, and with an etching gas atmosphere exclusively composed of chlorine, being implemented at a low-pressure. Compared to known ion etching processes, the method provides acceptable etching rates with a carbon-free, simple etching chemistry. The method is particularly useful for producing DRAMs with cell concepts of more than 4 Mbits.

Abstract: A process is provided for doping both sidewalls (26, 28) of isolation trenches (24, 26, 28) and connector regions (46, 48) between sources (58) and gate areas (62) and between drains (60) and gate areas in silicon CMOS devices. Appropriately doped glasses (16, 18, 30) formed on the silicon substrate (14) serve as the source of doping.

Abstract: A method for fabricating a bipolar or field effect-type integrated circuit transistor is provided in which non-cyrstalline semiconductor films and semiconductive regions formed in a single crystal semiconductor substrate and containing high concentrations of impurities are efficiently connected with improved electric characteristics while suppressing the influence of an increase in connection resistance caused by growth of a natural oxide film. Moreover, when a first non-crystalline semiconductor film is removed from a dielectric oxide film serving as a field film and a second non-crystalline semiconductor film is formed as a ribbon-shaped pattern on the exposed field film, a resistor of high accuracy can be formed. An interconnection system having resistors of a high accuracy and a fine size is also disclosed.

Abstract: A substantially planar dielectric wafer is formed by utilizing a polysilicon filler to remove surface irregularities (15, 15'). The polysilicon filler is formed by filling surface irregularities (15, 15') with polysilicon (19) and polishing the polysilicon (19) to form a substantially planar surface. A polishing stop (18) terminates the polishing and prevents damage to the wafer's isolated tubs (13). The polishing stop (18) can also be used as a mask during field oxide growth. The polysilicon filler also protects underlying areas (12) from subsequent etch operations. During subsequent field oxide growth, polysilicon layer (19) is converted to silicon dioxide which enhances dielectric isolation of each tub (13).

Abstract: A process for texturization of polycrystalline silicon comprising the steps of utilizing gas phase nucleation by injecting a material to a cause heterogeneous nucleation or by increasing deposition temperature or pressure to cause a homogeneous nucleation of the silicon source itself. Heterogeneous or homogeneous gas phase nucleation causes large, stable textures in the deposited polysilicon that can be doped using conventional fabrication techniques.

Abstract: A semiconductor device having a trench (30) comprises a semiconductor substrate (11), a plurality of elements (13) provided on the semiconductor substrate, a trench (30) provided between the elements and an insulating material (12) embedded in the trench for isolating the elements. The trench has its bottom portion region enlarged in both sides.The semiconductor device is manufactured by enlarging the bottom portion region of the trench by etching.

Abstract: A process for forming an insulating layer of silicon dioxide in a silicon substrate that surrounds and electrically insulates a semiconductor device is disclosed herein. The process comprises the steps of forming a recess on the outer surface of the silicon substrate that encompasses the site of the semiconductor device by photo-resist patterned reactive ion etching, and then removing silicon on the surface of the resulting recess whose crystal structure has been damaged by the reactive ion etching. Next, dopant atoms are selectively deposited on the surface of the recess so that the surface of the recess might be rendered into a porous layer of silicon when immersed in hydrogen fluoride and subjected to an electrical current. Prior to the porousification step, silicon is epitaxially grown within the walls of the recess to form the site for a semiconductor device.

Abstract: A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.

Abstract: Substrates polluted with toxic substances are treated in-situ with solvated electrons prepared chemically or electrochemically. The process is useful in treating porous and nonporous substrates, such as earth, clay, sand, soils, concrete, asphalt, wood, brick, block and other masonry surfaces, including liquids such dielectric fluids contaminated with halogenated hydrocarbons without the usual separation procedures to provide substrates suitable for recycle having <1 ppm pollutant remaining.

Abstract: A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.

Abstract: Disclosed is a catalytic process for hydroconverting heavy hydrocarbonaceous feedstocks to lower boiling products wherein a catalyst precursor concentrate or catalyst concentrate is first prepared in a heavy oil medium then fed to a hydroconversion zone which may also contain a supported hydrotreating catalyst. The hydroconversion zone may be operated in either slurry or ebullating bed mode.

Abstract: A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.

Abstract: A method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30 . Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Abstract: A microwave integrated circuit having planar and mesa components and microstrip lines and method of making the same is disclosed. To preserve a constant impedance for the microstrip lines, the mesa component is buried in a recess, which is then filled with a dielectric having substantially the same thermal expansion coefficient and the same dielectric constant as the insulating substrate. The surface of the mesa component and of the dielectric is in the plane of the planar part of the integrated circuit. Between the interconnecting microstrip lines on the planar face and the ground plane on the face of the substrate, the thickness and the dielectric constant of the material is constant.

Abstract: DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.