Patents Examined by G. Fourson
  • Patent number: 5081052
    Abstract: MISFET's are formed in the depletion mode in advance in a process comprising blanket implantation of the region in which memory cells are to be formed. MISFET's which are selected from these depletion-mode MISFET's are then formed into enhancement-mode or weak depletion-mode MISFET's to thereby write desired data into the memory cells of a read-only memory. The change of the MISFET's from the depletion mode into the enhancement mode (or weak depletion mode) is effected by introducing an impurity into the channel regions of the selected MISFET's in a manufacturing step that is carried out after the formation of the gate electrodes of the MISFET's.
    Type: Grant
    Filed: June 28, 1989
    Date of Patent: January 14, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Isamu Kobayashi, Ryuuji Shibata
  • Patent number: 5081061
    Abstract: A method including filling etched moats with a first dielectric layer and layer of polycrystalline material and planarizing. A second dielectric layer is formed on the first polycrystalline layer and a second layer of polycrystalline is formed on the second dielectric layer to form a handle. The starting material is then thinned to produce the dielectric isolated islands. Device forming steps are then performed. Finally, the handle is removed leaving a wafer having a thickness defined by the planarized surface of the first polycrystalline layer and the top surface of the first wafer.
    Type: Grant
    Filed: March 7, 1991
    Date of Patent: January 14, 1992
    Assignee: Harris Corporation
    Inventors: George V. Rouse, Paul S. Reinecke
  • Patent number: 5081058
    Abstract: An insulated gate field effect transistor surrounded by a field silicon oxide layer which is at least partially embedded in a silicon substrate, is disclosed. A pair of silicon oxide layers thinner than the field silicon oxide layer and thicker than the gate insulating film are formed on both end portions of the channel region in the channel width direction, and the gate electrode is formed on the gate insulating film and extends on the pair of silicon oxide layers and on the field silicon oxide layer.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: January 14, 1992
    Assignee: NEC Corporation
    Inventor: Masakazu Sasaki
  • Patent number: 5073509
    Abstract: A CMOS transistor is fabricated by forming the n-wells with both phosphorus and arsenic implants. The arsenic, with its lower diffusion coefficient, tends to concentrate near the top surface of the n-wells, with the phosphorus penetrating sufficiently to define the n-wells at the desired depth. A boron channel stop implant is later applied without masking over the n-wells. Since the arsenic implant is concentrated near the surface, the arsenic impurities overcome the effects of the boron impurities.
    Type: Grant
    Filed: December 11, 1989
    Date of Patent: December 17, 1991
    Assignee: Micron Technology, Inc.
    Inventor: Ruojia R. Lee
  • Patent number: 5070062
    Abstract: An oxychlorination catalyst is described which is constituted by porous particles of microspheroidal, or at least microcrystalline, alumina impregnated with cupric chloride and with the chloride of an alkali or alkaline-earth metal, in which the copper and the alklai or alkaline-earth metal are uniformly distributed over the entire surface area of the particles. The method for the preparation of the catalyst is also described. The catalyst enables oxychlorination of ethylene to dichloroethane to be achieved with improved fluodynamic behavior of the fluidized catalytic bed and with improved conversions and selectivity towards the useful reaction product.
    Type: Grant
    Filed: February 1, 1990
    Date of Patent: December 3, 1991
    Assignee: Enichem Synthesis S.p.A.
    Inventors: Roberto Canavesi, Ferdinando Ligorati
  • Patent number: 5068215
    Abstract: A multi-component oxide catalyst comprising zinc and an alkali metal is described which is useful particularly for converting methane and/or natural gas to higher molecular weight hydrocarbon products such as ethane and ethylene. The catalyst is characterized by the formulaZn.sub.a A.sub.b M.sub.c M'.sub.d O.sub.xwhereinA is Li, Na, K, or mixtures thereof;M is Al, Ga, Cr, La, Y, Sc, V, Nb, Ta, Cu or mixtures thereof;M' is Cs, Rb, Mg, Ca, Sr, Ba, Sm, Pb, Mn, Sb, P, Sn, Bi, Ti, Zr, Hf, or mixtures thereof;a is from about 1 to about 20;b is from about 0.1 to about 20;c is from about 0 to about 5;d is from about 0 to about 20; andx is a number needed to fulfill the valence requirements of the other elements; provided that(i) at least one of c and d is at least 0.1; and(ii) when M' is Sn, c must be at least 0.1.
    Type: Grant
    Filed: December 11, 1989
    Date of Patent: November 26, 1991
    Assignee: Standard Oil Company
    Inventors: Joseph P. Bartek, James F. Brazdil, Jr., John M. Hupp, Robert K. Grasselli
  • Patent number: 5068205
    Abstract: This invention provides a method for producing header mounted sensors, such as a chemically sensitive ISFET structures, which comprises steps which include providing a plurality of electrochemically sensitive ISFET sites on a semiconductor substrate with a source region, a drain region and an electrochemically sensitive gate region on the front of said substrate with contacts for said regions on the back of the substrate. A glass carrier, such as borosilicate glass is provided for the substrate. The carrier has a hole in it to maintain uncovered the contact areas of the ISFET sites and the carrier also has leads to provide electrical access to the area of the holes from the edges of the carrier. The substrate is electrostatically bonded to the glass carrier at the periphery of each of the ISFET sites and the boundaries of the individual ISFET sites are V-groove etched to form isolated individual silicon mesas each representing an individual ISFET structure.
    Type: Grant
    Filed: May 26, 1989
    Date of Patent: November 26, 1991
    Assignee: General Signal Corporation
    Inventors: Ronald D. Baxter, Paul M. Kroninger, Jr.
  • Patent number: 5059556
    Abstract: Method for relieving stress in silicon microstructures by forming a silicide on the microstructures. Sensors comprising a stress-relieved silicon microstructure are also described.
    Type: Grant
    Filed: March 16, 1990
    Date of Patent: October 22, 1991
    Assignee: Siemens-Bendix Automotive Electronics, L.P.
    Inventor: Duane T. Wilcoxen
  • Patent number: 5055420
    Abstract: After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.
    Type: Grant
    Filed: May 9, 1989
    Date of Patent: October 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Kouichi Nagasawa, Makoto Motoyoshi, Kiyoshi Nagai, Satoshi Meguro
  • Patent number: 5052421
    Abstract: The invention is a metal treating process which uses a chrome-free deoxidizing bath. The process is useful for cleaning and deoxidizing aluminum substrates followed by conversion coating of the cleaned and deoxidized substrates.
    Type: Grant
    Filed: July 27, 1990
    Date of Patent: October 1, 1991
    Assignee: Henkel Corporation
    Inventor: Mark W. McMillen
  • Patent number: 5051375
    Abstract: Disclosed is a method of producing a semiconductor wafer through gettering by means of sand blasting in a semiconductor wafer fabrication process. The method includes blasting abrasives each having a configuration at least similar to a sphere against a back surface of the semiconductor wafer, causing shear stress having a maximum point in the interior of the wafer to be generated, whereby damage is produced mainly in the interior of the wafer.
    Type: Grant
    Filed: July 10, 1989
    Date of Patent: September 24, 1991
    Assignees: Kyushu Electronic Metal Co., Ltd., Osaka Titanium Co., Ltd.
    Inventors: Sueo Sakata, Yasunori Oka, Toshio Naritomi
  • Patent number: 5051135
    Abstract: A cleaning method and cleaning system using an organic solvent such as Freon. A cleaning tank is closed after an article to be cleaned is placed within the cleaning tank. The solvent is supplied to the cleaning tank from a solvent storage tank. The article is cleaned with the supplied solvent. After the cleaning, the solvent is discharged in liquid state from the cleaning tank while vapor of the solvent which remains in the cleaning tank is discharged to a condenser to condense the vapor. The condensed solvent is returned from the condenser into the solvent storage tank. After the liquid solvent and vapor solvent are discharged from the cleaning tank, the cleaned article is taken out from the cleaning tank. The condenser is incorporated in a distiller. A solvent vapor supplying unit is connected to the cleaning tank. The thus provided closed system prevents release of Freon to the atmosphere.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: September 24, 1991
    Assignee: Kabushiki Kaisha Tiyoda Seisakusho
    Inventors: Masato Tanaka, Tadayoshi Ichikawa
  • Patent number: 5049521
    Abstract: A method for forming a dielectrically isolated semiconductor devices on a semiconductor substrate. An epitaxial layer is grown on a wafer having a thin buried oxide layer. Trench regions are etched through the epitaxial layer to the underlying oxide layer. A dielectric isolation layer is formed on the sidewalls of the trench regions so as to isolate an active region of the epitaxial semiconductor material. The trenches are etched to the underlying semiconductor substrate and the semiconductor material is selectively epitaxially regrown in the trench regions. Semiconductor devices are formed in the isolated active regions. Contacts are made to the active regions of the semiconductor device and to the wafer substrate through the epitaxially regrown trench regions.
    Type: Grant
    Filed: November 30, 1989
    Date of Patent: September 17, 1991
    Assignee: Silicon General, Inc.
    Inventors: Richard H. Belanger, Sang S. Kim
  • Patent number: 5045176
    Abstract: A vented cup ballistic separation device and method of use for achieving rapid separation of a suspension of fluidized solid particulate and gasiform material. The vented cup ballistic separation apparatus is useful in a wide variety of vapor-solid contacting devices where rapid separation of solids from vapor is desired e.g. in fluidized catalytic cracking systems. The vented cup ballistic separation apparatus particularly comprises annular chamber about the outer periphery of an open ended riser conduit. The annular chamber is open in the upper end and one or more open end conduits extend outwardly from the annular chamber to provide means for discharging vapors and also for attachment of cyclone separation means if desired. The riser with vented cup or annular chamber preferably terminates within a larger diameter chamber.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: September 3, 1991
    Assignee: Ashland Oil, Inc.
    Inventors: Paul W. Walters, Roger M. Benslay, Dwight F. Barger
  • Patent number: 5043522
    Abstract: The present invention relates to the conversion of saturated paraffin hydrocarbons having 4 or more carbon atoms to olefins having fewer carbon atoms. In particular, the invention provides for contact of a mixture of 40 to 95 wt % paraffin hydrocarbons having 4 or more carbon atoms and 5 to 60 wt % olefins having 4 or more carbon atoms with solid zeolitic catalyst such as ZSM-5 at conditions effective to form propylene and the separation of light olefins from the reaction mixture.
    Type: Grant
    Filed: March 27, 1990
    Date of Patent: August 27, 1991
    Assignee: Arco Chemical Technology, Inc.
    Inventors: David W. Leyshon, Glenn E. Cozzone
  • Patent number: 5043500
    Abstract: A dehydrogenation process, where a hydrocarbon feed is dehydrogenated in a dehydrogenation zone and then oxidatively reheated by the combustion of hydrogen in an oxidation zone containing an oxidation catalyst, is improved by using a stream of dilution steam as an educing fluid to draw oxygen into contact with the effluent from the dehydrogenation zone ahead of the oxidation zone. A stream of dilution steam is often combined with the dehydrogenation zone effluent in order to control the oxygen concentration ahead of the oxidation zone and to lower the hydrogen partial pressure. Educing the oxygen-containing gas for the oxidation zone into the process by using the dilution steam an an educing fluid eliminates the need for compression of the oxygen-containing gas and prevents oxygen from contacting the dehydrogenation zone effluent before the dilution steam is admixed therewith. This process is particularly beneficial in the dehydrogenation of ethylbenzene to produce styrene.
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: August 27, 1991
    Assignee: UOP
    Inventor: Constante P. Tagamolila
  • Patent number: 5036023
    Abstract: The inventive method of producing a device having non-alloyed ohmic contacts of common composition to both an n-doped and a p-doped region of a semiconductor body comprises deposition of a Ti/Pt layer on the p-doped as well as the n-doped region, followed by rapid thermal processing (RTP). Exemplarily, the device is a semiconductor laser, the n-doped region is InP, the p-doped region is InGaAs or InGaAsP, and RTP involves heating in the range 425.degree.-475.degree. C. for 10-100 seconds. The method comprises fewer processing steps than typical prior art methods, reduces the danger of fabrication error and of wafer breakage and, significantly, results in contacts that can be relatively thermally stable and can have very low specific contact resistance (exemplarily as low as 10.sup.-7 .OMEGA..multidot.cm.sup.2).
    Type: Grant
    Filed: August 16, 1989
    Date of Patent: July 30, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: William C. Dautremont-Smith, Avishay Katz, Louis A. Koszi, Bryan P. Segner, Peter M. Thomas
  • Patent number: 5034346
    Abstract: A method is disclosed for forming a shorting contact for shorting P-type and N-type conductivity regions in a semiconductor together. In one embodiment of this method, the P-type region is substantially a square and is surrounded by the N-type region. A substantially square contact opening is made to expose the P-type region and a portion of the N-type region. Sides of the contact opening are formed to be at substantially 45 degree angles with respect to sides of the substantially square P-type region. In this manner, the alignment tolerance for forming the contact opening is less critical than if the sides of the contact opening were parallel to the sides of the P-type region. The contact opening is then filled with a conductive material to electrically short the P-type region to the N-type region. The conductivity types in this example may be reversed.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: July 23, 1991
    Assignee: Micrel Inc.
    Inventors: Martin J. Alter, Clyde M. Brown, Jr., James B. Compton
  • Patent number: 5019661
    Abstract: Branched olefins of at least 4 carbon atoms are hydroisomerized to a less branched alkane by contact with a hydrogen containing gas and a shape selective zeolite which has at least 1 metal of the Pt group supported primarily within the channels of said zeolite.
    Type: Grant
    Filed: June 1, 1989
    Date of Patent: May 28, 1991
    Assignees: Commonwealth Scientific and Industrial Research Organisation, Broken Hill Proprietary Company Limited
    Inventor: Thomas Mole
  • Patent number: 5013693
    Abstract: Micromechanical structures having surfaces closely spaced from surfaces of a substrate are formed using normal wet etching techniques but are not dried in a conventional manner. While the substrate with the microstructures formed thereon is still wet, the substrate is covered with a liquid that can be frozen, such as deionized water. The liquid on the flooded structure is then frozen in a well controlled manner such that freezing is completed before the microstructure is uncovered. The microstructures are therefore undeflected and are covered by a solid on all surfaces. This solid is then sublimated at a predetermined temperature. Because the frozen liquid (e.g., ice) supports its own surface tension, the microstructures are not drawn toward the substrate, as occurs with the drying of liquids. The sublimation of all the frozen liquid leaves undeflected microstructures with no permanent bonding of the facing surfaces of the microstructure and the substrate.
    Type: Grant
    Filed: February 16, 1989
    Date of Patent: May 7, 1991
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Henry Guckel, Jeffry Sniegowski