Abstract: A request to access a virtual tape volume is identified and a lock status is maintained for the virtual tape volume. The lock status includes a shared status and an exclusive lock status. In shared status, it is determined whether the request includes a request for write access to the virtual tape volume. Concurrent access to the virtual tape volume can be allowed by two or more applications during the shared status based at least in part on whether the applications request for write access to the virtual tape volume.

Abstract: A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.

Abstract: Disclosed herein are system, method, and computer program product embodiments for virtual machine (VM) backup from a storage snapshot. An embodiment operates by receiving selective backup parameters including a VM to backup and then creating a VM snapshot associated with the VM. Next, an offset table associated with a virtual disk of the VM stored on a storage is retrieved. The embodiment further includes generating a storage snapshot and deleting the VM snapshot and then promoting the storage snapshot to a new logical unit number. The promoted storage snapshot is then mounted to the backups server. The virtual disk data is backed up to a backup storage using the offset table from the storage snapshot. The storage snapshot is dismounted from the backup server and deleted from the storage.

Abstract: The embodiments disclosed herein provide a flash aware snapshot technique for two-way data recovery and back-in-time execution. The disclosed snapshot technique is designed to reduce the number of write operations to improve the performance on flash-based storage systems. The disclosed snapshot technique can guarantee data recovery no matter which of the production site or the backup site fails. The disclosed snapshot technique can also reduce the storage space requirement for snapshots by exploiting content locality. Furthermore, the disclosed snapshot technique can be implemented using hardware, software, firmware, or any combination of them. In case of hardware implementation, only minor hardware modifications are needed.

Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.

Abstract: Exemplary methods for managing cache based on approximate least recently used (LRU) cache entries include maintaining a distributed data structure (DDS) of data elements, each corresponding to a cache entry of a plurality of cache entries, wherein each data element can be atomically accessed by multiple threads. In response to a cache eviction request from a first thread, determining an approximately LRU cache entry among the cache entries based on values atomically accessed from a first subset of the DDS of data elements, wherein the first subset of the DDS is atomically accessed using an atomic instruction without acquiring a lock to prevent another thread from accessing the first subset of the DDS to determine other approximately LRU cache entries among the cache entries, while allowing a second thread accessing a second subset of the DDS substantially concurrently. Evicting the determined approximately LRU cache entry.

Abstract: A communication apparatus and method based on shared memory are disclosed. The communication apparatus based on shared memory includes a data publication unit, a data subscription unit, and an access control unit. The data publication unit publishes data stored in a shared memory unit. The data subscription unit subscribes to the data stored in the shared memory unit. The access control unit controls the access of the data publication unit and the data subscription unit to the shared memory unit in response to locking operation instructions of the data publication unit and the data subscription unit with respect to the shared memory unit.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: Methods, systems, and computer readable media for solid state drive caching across a host bus are disclosed. According to one aspect, a method for solid state caching across host bus includes, during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bust interface for accessing a second RAM memory located on a host and separate from the first RAM, using the first RAM as a cache for storing a first portion of metadata, and using the second RAM as a cache for storing a second portion of metadata, where the second RAM is accessed by the SSD via the host bus interface.

Abstract: According to some embodiments, a method for controlling a processor state with transient cache memory is described. The method may include identifying, via a processor, a memory section having a memory address, retrieving, via the processor, memory control information, and controlling the processor state by allowing a memory access to the transient cache memory based on the memory control information.

Abstract: An information processing apparatus includes a free page storage unit and a page allocating unit. The free page storage unit divides a memory region in a memory into pages of a plurality of different page sizes and manages the divided pages, and stores management information about an initialization state corresponding to an unused memory region in the memory. The page allocating unit selects a free page of a page size according to a requested region size or a requested page size from the free page storage unit when an allocation of the unused memory region is requested, and performs an initializing process on a memory region on which the initializing process has not been performed in a memory region corresponding to the free page using management information about the selected free page.

Abstract: Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.

Abstract: A computer-implemented method includes receiving a request to access a cache entry in a shared cache. The request references a synonym for the cache entry. A cache directory of the shared cache includes, for each cache entry of the shared cache, a first-ranked synonym slot for storing a most recently used synonym for the cache entry and a second-ranked synonym slot for storing a second most recently used synonym for the cache entry. The method includes, based on receiving the request, writing contents of the first-ranked synonym slot for the cache entry to the second-ranked synonym slot for the cache entry, and writing the synonym referenced in the request to the first-ranked synonym slot for the cache entry.

Abstract: A method for setting up and managing large numbers of storage volumes is disclosed. In one embodiment, such a method enables a user to establish a volume class comprising various volume attributes. The method further enables the user to assign a volume or range of volumes to the volume class. Once the volume or range of volumes is assigned to the volume class, the method automatically sets up, without user invention, the volumes with the attributes designated for the volume class. When a new volume is assigned to the volume class, the method automatically sets up the new volume with the attributes of the volume class, including automatically calculating a VTOC size for the new volume based on VTOC sizes for volumes already assigned to the volume class. A corresponding apparatus and computer program product are also disclosed.

Abstract: A method for resource management of a data processing system is described herein. According to one embodiment, a token is periodically pushed into a memory usage queue, where the token includes a timestamp indicating time entering the memory usage queue. The memory usage queue stores a plurality of memory page identifiers (IDs) identifying a plurality of memory pages currently allocated to a plurality of programs running within the data processing system. In response to a request to reduce memory usage, a token is popped from the memory usage queue. A timestamp of the popped token is then compared with current time to determine whether a memory usage reduction action should be performed.

Abstract: Exemplary methods for minimizing contention among multiple threads include maintaining a plurality of linked lists of elements, each linked list corresponding to one of a plurality of threads accessing cache entries, each element of each linked list corresponding to one of the cache entries, wherein each linked list comprises a head element and a tail element, the head element corresponding to a most recently used (MRU) cache entry among all cache entries accessed by a corresponding thread, and the tail element corresponding to a least recently used cache entry among all cache entries accessed by the corresponding thread. In response to a cache eviction request, determining a LRU cache entry among the plurality of cache entries based on values accessed from one or more of the tail elements of the linked lists, and evicting the determined LRU cache entry by populating the determined LRU cache entry with the new data.

Abstract: According to one embodiment, there is provided a memory system that is connected to a host apparatus. The memory system includes a transmitting port and a controller. The transmitting port transmits a transmission signal to the host apparatus. The controller includes a first output interface that is connected to the transmitting port and a second output interface that is connected to the transmitting port. The memory system is configured such that a drivability of an output from the first output interface is larger than a drivability of an output from the second output interface in a first mode.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.