Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

Abstract: In an information processing system including a set of data storage devices for storing data blocks arranged in respective columns on each data storage device and rows across the set of data storage devices to form at least one data stripe, and a set of parity storage devices for storing parity blocks computed via one or more parity operations based on the data blocks of the at least one data stripe, at least one of the data storage devices includes a processing device configured to: receive from the information processing system an instruction to perform at least a portion of a parity operation; perform the portion of the parity operation; and send a result of the performed portion of the parity operation to the information processing system, wherein the result is useable by the information processing system for performing another portion of the parity operation.

Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as single bit per memory cell data to increase the performance of the programming process. Subsequently, the control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data.

Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Abstract: A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates is provided. The concurrent faults occurring in the CMOS circuits are detected without being masked by the method. The method includes the following steps: Carrying out functions using the reversible gates and the preservative gates, transforming the reversible gates and the preservative gates into CMOS circuit equivalents.

Abstract: Systems and methods are provided for reducing error in data compression and decompression when data is transmitted over low bandwidth communication links, such as satellite links. Embodiments of the present disclosure provide systems and methods for variable block size compression for gridded data, efficiently storing null values in gridded data, and eliminating growth of error in compressed time series data.

Abstract: A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly comprises a memory die bonded to a control die with bond pads. The control die includes one or more control circuits for controlling the operation of the memory die. The one or more control circuits are configured to receive data to be programmed into the memory die, select a number of parity bits, encode the data to add error correction information and form a codeword that includes the number of parity bits, shape the codeword, and program the shaped codeword into the memory die.

Abstract: A debug support device includes: a root device extraction unit that extracts, from a sequence program that includes a circuit block including a plurality of devices, a result device on the basis of an association between a factor device that contributes to determination of a value of another device and the result device having the value determined by the factor device; a related device retrieval unit that retrieves, as a related device, each and every one of the factor device(s) that determines the value of the result device; and a display control unit that outputs group information to a display device. The group information is information on a group, associating the result device, the value of the result device, the related device, and a value of the related device.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.

Abstract: An autonomous RAID data storage device locking system includes first RAID data storage device(s) that store data included in a data stripe, and that are coupled to a second RAID data storage device. The second RAID data storage device receives a command to perform a data update operation on a subset of data included in the data stripe, and transmits a locking request to each first RAID data storage device. When the second RAID data storage device receives a locking confirmation that indicates that each first RAID data storage device is locked, it completes the data update operation on the subset of data included in the data stripe. The second RAID data storage device then transmits an unlocking request to each first RAID data storage device to cause them to unlock, and transmits a completion communication that indicates that the data update operation has been performed.

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform an error correction on data read from a memory region of the non-volatile memory, and set a value of a parameter corresponding to a number of parity bits to be added to write data to be written into the memory region based on a number of data bits corrected in the error correction of the read data in a case where the error correction is successful.

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.

Abstract: A system for aggregating dataflow lineage information is disclosed. The system receives one or more input data elements and determines a dataflow path for the one or more input data elements. The dataflow path includes at least a data storage node and a computation node. Then, the system identifies a lineage control value associated with the data storage node and a version control value associated with the computation node. The system generates an output lineage for the one or more input data elements by appending the lineage control value to the version control value.

Abstract: A method of detecting leakage of a data qubit includes applying a first cross-resonance pulse to the data qubit, the data qubit including a first state and a second state; applying a first echo pulse to the data qubit temporally following the applied first cross-resonance pulse; applying a second cross-resonance pulse to the data qubit temporally following the applied first echo pulse, the second cross-resonance pulse being an inverted form of the first cross-resonance pulse; applying a second echo pulse to the data qubit temporally following the second cross-resonance pulse; and detecting a leakage associated with the data qubit using an ancilla qubit coupled to the data qubit based on application of the first and second cross-resonance pulses, and the first and second echo pulses.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.