Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.

Abstract: A micro device includes a securing layer, a plurality of micro device units that are separated from each other and that are spaced apart from the securing layer, and a connecting layer that interconnects the micro device units in at least one group of two or more and that is connected to the securing layer so that the micro device units are connected to the securing layer through the connecting layer. A method of making the micro device is also provided.

Abstract: A semiconductor device according to an embodiment includes a stacked body having first films and second films that are alternately stacked, a light shielding film provided in a specific layer of the stacked body and having a higher optical absorptivity than that of the second films, and a channel film extending in the stacked body in the stacking direction. The channel film includes a first part located on an upper side than the light shielding film in the stacking direction and containing a monocrystalline semiconductor.

Abstract: According to one embodiment, a semiconductor device includes a memory region and a peripheral circuit region, the peripheral circuit region includes a first region and a second region outside of the first region. The semiconductor device includes, in the first region, a transistor including a gate insulating layer and a gate structure that includes a gate electrode. A first structure is in the second region and includes a first insulating layer and a dummy gate electrode on the first insulating layer. The first insulating layer has a side surface facing outward from the peripheral circuit region and a second insulating layer that covers the first side surface and is an insulating material other than a silicon oxide.

Abstract: In a display device including a pixel arranged therein, the pixel including a light emitting unit in which an anode electrode is formed in the uppermost layer of a multilayer wiring structure formed by alternately stacking a plurality of insulating layers and a plurality of wiring layers, and a capacitor element electrically connected to the anode electrode of the light emitting unit, or in an electronic device including the display device, the capacitor element including a first electrode formed in a wiring layer below the anode electrode, a second electrode formed opposite to the first electrode, and attached to the anode electrode of the light emitting unit via a conductive rib, and a first insulating layer interposed between the first electrode and the second electrode.

Abstract: A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.

Abstract: A memory device includes a bottom electrode, a conductive layer such as an alloy including ruthenium and tungsten above the bottom electrode and a perpendicular magnetic tunnel junction (pMTJ) on the conductive layer. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet on the tunnel barrier. The memory device further includes a synthetic antiferromagnetic (SAF) structure that is ferromagnetically coupled with the fixed magnet to pin a magnetization of the fixed magnet. The conductive layer has a crystal texture which promotes high quality FCC <111> crystal texture in the SAF structure and improves perpendicular magnetic anisotropy of the fixed magnet.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure; a source structure; a channel structure penetrating the stack structure, the channel structure being connected to the source structure; and a first memory layer interposed between the channel structure and the stack structure. The source structure includes a first protrusion part protruding between the first memory layer and the channel structure.

Abstract: A method for forming a three-dimensional (3D) memory device includes forming a cut structure in a stack structure. The stack structure includes interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers. The method also includes removing portions of the stack structure adjacent to the cut structure to form a slit structure and an initial support structure. The initial support structure divides the slit structure into a plurality of slit openings. The method further includes forming a plurality of conductor portions in the initial support structure through the plurality of slit openings. The method also includes forming a source contact in each of the plurality of slit openings. The method also includes removing portions of the initial support structure to form a support structure. The support structure includes an adhesion portion extending through the support structure.

Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.

Abstract: A semiconductor device according to an embodiment may include: a light emitting structure; a light transmitting electrode layer disposed on the light emitting structure; and a reflective layer disposed on the light transmitting electrode layer and including a plurality of first openings and a plurality of second openings. The semiconductor device according to the embodiment may include: a first electrode in contact with a first conductivity type semiconductor layer of the light emitting structure; and a second electrode in contact with the light transmitting electrode layer through the plurality of first openings.

Abstract: A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.

Abstract: A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.